Hi,
according to the new Virtex-II Platform User Guide the major address of a CLB goes from 4 to n+4 (with n CLB columns). If you have a module located on such an FPGA can one say that the major addresses of this module are contiguous? I guess the VirtexE has an addressing where neighboured CLBs have a mja-delta of 2. The User Guide also says: "During configuration, frames are programmed in order of increasing block, major, and minor address[...]" p.317
Thanks for any kind of information. Regards Chris