I see two issues here looking for the classical design practices.
Consider a solution space scanner feeding a N-stage pipeline calculating the quality of the solution. As soon as the quality appears satisfactory, we stop the pipeline and show the solution to the user. How do you determine which data was entering the pipeline just N steps earlier?
[space explorer] || || (solution) \/ [stage 1] || \/ [stage 2] ... || \/ [stage n] || || (quality) \/ [constraint analyzer]One of the opportunities would be to supply a "solution" tag to each pipeline stage. Nevertheless, the solution may take large room (8 bytes in my case x16 stages, could be not too much for an FPGA?). Another option would be to exploit the knowlenge of current solution entering the pipe. As we know there is N stages we can roll N solutions back (topSol = EnteringSol - N) and calculate the one at the top of the pipeline.
Another question is related to activating the pipeline-listening logic. As there is N-stage latency, the output will be not valid during that period and the [constraint analyzer] should be sleeping.
Please give me the clues, thanks in advance, any references appreciated.