Maintaining a Pipeline

I see two issues here looking for the classical design practices.

Consider a solution space scanner feeding a N-stage pipeline calculating the quality of the solution. As soon as the quality appears satisfactory, we stop the pipeline and show the solution to the user. How do you determine which data was entering the pipeline just N steps earlier?

[space explorer] || || (solution) \/ [stage 1] || \/ [stage 2] ... || \/ [stage n] || || (quality) \/ [constraint analyzer]

One of the opportunities would be to supply a "solution" tag to each pipeline stage. Nevertheless, the solution may take large room (8 bytes in my case x16 stages, could be not too much for an FPGA?). Another option would be to exploit the knowlenge of current solution entering the pipe. As we know there is N stages we can roll N solutions back (topSol = EnteringSol - N) and calculate the one at the top of the pipeline.

Another question is related to activating the pipeline-listening logic. As there is N-stage latency, the output will be not valid during that period and the [constraint analyzer] should be sleeping.

Please give me the clues, thanks in advance, any references appreciated.

Reply to
valentin tihomirov
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Does it make sense to stick a circular buffer of size a bit bigger than N at the top of the pipeline, and tag each entry with a short quantity indicating where in the buffer its input is stored? Reduces the amount you have to carry down the pipeline, though the circular buffer is a small wide memory which might be inefficient in the FPGA world of large narrow memories.

Tom

Reply to
Thomas Womack

In my case, the pipeline input is not stored at all. However, it will be needed at the moment the pipeline produces the output for that input. Any recommendations?

Reply to
valentin tihomirov

The stat(g)es of a pipeline constantly applied to the same input sequence can be statically initialized so that the output is valid immediately. That is, no need to wait N cycles. However, the initalial stage computation can complicate the VHDL code considerably, so I am not sure this approach is decidedly more advageous than merely flagging "invalid" N first outputs of the pipeline.

Reply to
valentin tihomirov

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