Hello everybody,
I need help in dealling with hard macros (in vhdl). I want to instantiate my macro in a vhdl design.
any one have an idea how to do it ? I tied to do as instantiating vhdl modules but the synthesizer does not recognize my macro.
Plz help.
thanks in advance.
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--Mlle Molka BEN ROMDHANE
--Doctorante Comelec
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