LVTTL, LVCMOS or 3.3V-PCI?

I guess LVTTL is the low voltage version of the ordinary TTL, low current source (none !) but high current drain. LVTTL comes in 3.3 Volts an

2.5Volts, and I guess the source-drain issue goes for them as wel.

LVCMOS are the low-voltage version of the normal cmos, it has equal drain and source current, ant thats that.

3.3V PCI- i am not sure of, but I guess LVTTL at 3.3V should do the trick I use LVCMOS at 2.5V level to source diodes and stuff on my board, but i guess PCI has somewhat legacy til TTL, so I guess this is the better choise for this interface.

kia rui schrieb:

These signalling standards define different worst case output voltages, input thresholds and a couple of other parameters that the IO pins must adhere to. A 3.3V CMOS IO more or less automatically fulfills the LVTTL standard, so the FPGA is likely to be configered identically no matter what you select. The only difference is that the timing analyzer software is told to use different voltage thresholds to define timing.

PCI3.3 might also be the same drivers, maybe with adjusted slew rate. When you select PCI3.3 the timing analyzer will report slower delays because PCI defines timing for a rather high output load of 50pF.

Kolja Sulimma