LVDS without termination

termination.

really

complicated

driving

output

This may depend on the drivers, but what I've seen from standard quad driver chips is that the outputs will eventually drive near the rails, in your case 3.3V or ground. Realize that initially the driver is limited by its impedance and the characteristic impedance of the driven lines even though they are not terminated. For longer lines the voltage at the driver will rise in small steps separated by the round-trip delay time. For short lines you'll see more of a ramp. I wouldn't expect much overshoot due to the current limit of the drivers, however I would expect problems running at 480 Mbps NRZ. You may not have a problem with clock lines, but if data is in one state for several bit periods, the voltage that develops may prevent the next signal transition from happening fast enough.

a

For short lines I would say this is a reasonable approach and will work much better than no termination.

1st) AFAIK LVDS without termination does not work, since the outputs are CURRENT mode, without a termination no clean output voltage. 2nd) you have Saprtan-3 which has DCI, Digital Controlled Impedance, so no need for external termination, this can be done inside the FPGA.

Regards Falk

Kolja, Oh dear, what claptrap you've had so far in response to your query. IMHO of course! I guess you get what you pay for! Anyway, here's my guff. The data rate is somewhat unimportant. What's the rise time of the signals into your spartan3? Can you tell us what the driving part is? Also, you should be aware that the trace length on the PCB is only part of the signal path. There's also the leadframe/BGA package to consider. A rule of thumb from that Howard Johnson chap, if the total signal path is less than a sixth of the rise time, you're OK! Electric goes at about 160ps/inch. Cheers, Syms. BTW, LVDS/PECL/CML etc. can work without a termination resistor, and the DCI thing has 'issues'. Browse the Xilinx answers thingy.

From what I read on this newsgroup LVDS_25_DCI essentially does not work if you have many inputs. At least it is not worth the hassle. (Webpower estimates 740mA supply current for 16 LVDS_25_SCI inputs at

480 Mbps).

All the other DCI modes seem to be OK.

Kolja Sulimma

Well, it gives you an upper bound on the rise time.

What's the rise time of the signals

They are programmable from 150ps to 400ps.

ADS5270

Thanks. I am pretty sure that I can disregard transmission line effects at these very short signal lengths. What I am concerned about is the current mode driver characteristic as described by Gabor.

Kolja

part of

consider. A rule

less

160ps/inch.

effects

The parts I was referring to are DS90C031 quad drivers, which are sort of jelly-bean parts in a package pin-compatible with the venerable AM26LS31. These are much slower than the ADS5270 but do have current source outputs and will drive near the rails with no terminating resistor. What bothers me about leaving out terminators, especially in your case where you're not running 8b/10b or some other code with guaranteed AC content, is what happens when the output has been in one state long enough to generate a wide voltage spread. By the way, LVDS drivers in FPGA's are not current mode and wouldn't have this problem. It may be worth experimenting with the ADS5270 if you have a chance to hook one up without a load (maybe on an evaluation module) to see what the outputs do without termination. It would also be interesting to see how the TI evaluation module handles termination. The appnotes for the reference design from the Xilinx site don't mention the PC board issues.

If you can live with the power hit and other quirks, it works.

On S3, with the new DCIUpdateMode=Quiet setting, the bank-bank offset problem should go away. ( although with differential inputs, that only offsets the common mode of the differential input buffer, which might(?) have minimal effects on the prop. delay )

Watch the FPGA Cin reflections if you need to get that forwarded clock to both a local clock input and a global clock input- offhand, I'd do a flyby of the local clock pins (delay matched to the data lines) with isolation resistors feeding the local clock input, on to the global clock pins with provision for a differential attenuator ahead of the global inputs to damp out the reflection there.

Watch those mA and mW :)

When I checked just now, Webpower still gives a hopelessly low static VCCO power estimate of 74 mW per bank overhead and 31 mW per input pair for S3.

For V2, I found 200 mW per bank and 100 mW per pair far more realistic estimates of static LVDS_25_DCI power overhead (50 ohm VRP/VRN).

No, all the parallel split termination modes have high power by their nature.

On a short run, you could try increasing the value of VRP/VRN to maybe

75-100 ohms and see how things look in simulation.

Another possibility to eliminate the per-bank overhead would be to try disconnecting the VRP/VRN resistors with a timed analog switch after configuration once the DCI updates have stopped.

Brian

Oops, that should have read "31 mw per input pin" not "per input pair"; i.e., they still seem to be using the 62.5 mW per pair DCI overhead number in the WebPower estimator tools.

Brian

Hi Gabor, I think the point is, that with tiny loads on the output, i.e. small traces, the outputs swing very quickly to whatever voltage the current sources can provide. This probably remains within the range of the FPGA's diff inputs, they're very good and wide. I don't see how having 'guaranteed AC content' makes any difference. Could you explain what you mean by that? Do you mean enough edges, or no DC? As you say, I'd certainly have to try it first, the datasheet is not clear on the output structure. See appnote HFAN-01.0 from Maxim for an overview of their output structure. Dunno what the Texas one looks like. On the other hand, I'd be very nervous about doing this. Especially with an enormous 80 pin PQFP package driving the outputs. Again, think of the hideous leadframe. Like you say, you'd have to prototype it first. Kolja, You do know that you can get 8x100 resistors in two packs sized 2x1mm? Rohm, AVX, Koa etc.. have gone to a lot of trouble to make these bits. Use them!

And fix your PCB technology, your competitors will! Cheers, Syms.

traces,

sources can

inputs,

content'

mean

My point is that whether you model the lines as 50 ohm transmission lines with some finite delay, or as a lumped capacitive load, you will see that a current source switched into this net provides a slew-rate limited output. The slew rate should come directly from the current value and the effective capacitance. So if you had an ideal current source that never clipped, and didn't have a DC balanced code, you would slowly integrate to one state or another and never return to the zero crossing. In the case of a voltage-limited source, the issue is how much longer does it take to reach the crossover threshold if the outputs have a 2V differential (no load case having been in one state long enough to clip the current source) than it would to reach the crossover from a 0.35V differential (nominal LVDS into 100 ohms). If the slew-rate limits you to a value that you can't accept at 480 Mbps you will need the resistors, not for termination but to limit the output voltage swing. For a true current source for example at 3.5mA going into 10 pF, you would slew at most 0.35V per nanosecond. From the data sheet specs like ISOUT NP (outputs shorted together gives

12 mA max) I would guess these "current outputs" are not true current sources, so the slew time may not be that bad. However if the output were really limited to 3.5 mA you could see that trying to slew 2V would put you out of the realm of achieving 480 Mbps. You may find that the drivers don't behave this way, but putting pads for the 100 ohm terminators (even near the source) would give you a way out if they do.

clear

overview of

with an

2x1mm? Rohm,

them!

the

case

long

What's your planned routing scheme for the short differential nets? ( i.e. track width/separation/height/etc per pair and between pairs, # layer changes, # vias per net )

Also, if the A/D is only 4 mm distant from the FPGA, I'd start worrying about power/gnd plane noise & bypass problems, and then start considering moving it farther away :)

Or, are you splitting A/D and FPGA ground & power to provide supply isolation, and then running coupled pairs across the plane cuts to the FPGA?

As for the unloaded behavior, I believe the driver output impedance requirements (IIRC about 40-140 ohm single ended ) of the LVDS specs should bound the unloaded output swing. ( I'd add a third vote for the recommendation of verifying that with your actual driver on an eval board )

I'd also vote for the suggestion of at least leaving room for terminations where you can fit them near the driver; or, if the pairs are crossing a plane cut, perhaps a fancier differential/common mode attenuator scheme located right at the plane cut would be in order.

If you have output driver strength control, you can tweak that to reduce the output swing, whether unloaded or into a higher-than-normal DCI termination value.

Brian

On a short run, just where the termination is, is not as critical as having the temination itself.

Fish-hooks in no termination at all, are likely to be : a) Common mode range of the LVDS receivers - I do not believe this is Rail-rail comparitor stuff - outside the common mode range two things might happen - slower recovery and/or logic inversion. Someone at xilinx should know ?

b) Simple dV/dT effects, will mean more intersymbol distortion effects [assuming a) does not bite you first :) ]

you can get 4 resistors in a single package, and mount them routing-practical distances from the receiver ?

-jg

Ah well, here I go. This may generate some traffic. Don't split the ground plane. Ever. It's your reference. I hear all this stuff about currents flowing through the plane giving voltage noise. Doesn't matter, with _proper_ bypassing, everything is coupled to the ground plane so it all goes up and down locally with the plane anyway. Separate power is of course a good idea, and in fact probably necessary. Each power area is isolated from other power areas but tightly coupled to the ground plane locally. As for your digital signals, keep them close to the ground plane all the way to their destination. Occasionally you'll see an app note from a ADC vendor saying you can use a split plane, but all their sample/demo boards always have a single non-split plane. I've come to think this is because they want to keep die-hard plane-splitters using their parts. I guess these customers make a LOT of prototypes! Cheers, Syms. p.s. Hey Kolja, did you look at those resistor packs?

Just to clarify, I'm not saying a split plane won't work. I'm saying that with proper bypassing/decoupling it won't work any better than a single plane. Cheers, Syms.

I didn't intend to wholeheartedly endorse splitting up the ground plane, but only to question how Kolja was planning to lay out the board, and suggest that appropriate care and attention be paid if attempting such a crossing with the LVDS pairs in question.

Brian

Thanks to all of you for your replies. I am going to squeeze in the resistors somehow (the problem is to fit all the vias).

Kolja Sulimma

Jim Granville wrote

[...]

Yes I did. I used them in previous projects. The problem with this one are the vias. I can run differential pairs nicely pitch matched from the 0.5mm pitch pqfp to the 1mm bga. Now 0.5mm single in line resistor packs would be graet (Pinout A1-A2-B1-B2-....). But dual in line resistor packs are rather useless unless I can route a signal between the pins.

I can't meet a 0.5mm via pitch, so the resistors can not sit at the back . And I can not have the vias on the inside of the PQFP (at least not all of them) because it is almost completely filled with a thermal pad.

But I am going to find a way to squeeze in the resistors....

Kolja

one

pitch

back

pad.

Check out Bourns CAT16-PT4F4 or CAT16-PT2F2. These are 0.8mm, not 0.5 but they route through nicely on the surface (they're DIP but work like a SIP because opposite pads connect together).

You are aware that I need to do parallel termination, not series termination? I use these resistor arrays a lot, but as you can not route between the pins they are really inconvenient for LVDS parallel termination.

But we are really OT for this group now. Is there a sci.pcb.layout newgroup or something? ;-)

Kolja