LVDS termination scheme to nonstandard ribbon cable

Hi

I am doing a Spartan3 to Spartan 3 interconnect trough a ribbon (flat) cable with a characteristic impedance of 173R balanced (103R unbalanced). I have tried xilinx webcase to answer on the termination requirements of LVDS for spartan 3 withhout much luck. I got 2 different answers.

My questions are:

1) Can I use a ribbon cable with 173R balanced characteristic impedance? I have read that it should be 100R. The transmission is rather short, 300mm and relative slow in lvds terms. I would rather not switch the cable since it have other good properities that I rely on.

2) With the above cable should the receiver end termination still be

100R

3) With the above cable is a source resistor network necessary to match the impedance on the transmitter side and lower reflections? This is the point where xilinx tend to confuse itself in its datasheets for spartan 3. My dirty solution with adding 150R series resisor tend to give nicer signals.

Hope someone could help me on this.

Thanks in advance

Reply to
stefan.elmsted
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Yes.

No. It should match the cable.

No, it's not necessary. If the receiver is properly terminated, there should be no reflections.

BTW, the impedance of the cable seems high. What cable are you using, and in what mode? I.e.

GSGSGS or GSSGSSG or has the cable got twisted pairs?

G = ground, S = signal.

Cheers, Syms.

Reply to
Symon

The receiver should be the differential impedance of the cable and of the transmitter - they should all (roughly) match. If you have an external termination at the receiver, change it to the 173 ohm value if that's the true differential impedance. If the termination is internal at 100 ohms, add two 36 ohm resistors (or thereabouts) to get the impedance match, albeit at a reduced signal amplitude.

On the transmitter, you want a 100 ohm to 173 ohm impedance match so the transmitter sees 100 ohm but the transmission line sees 173 ohm. You'll need a differential termination on the transmitter side of this network and two series resistors to the ribbon cable. The signal amplitude will again be reduced.

If the doubly-reduced signal amplitude is a problem, your slower speed will allow a different approach. Rather than using the native 100 ohm LVDS transmitter, step back a couple years and use a three-resistor network to match 2.5V differential outputs to the LVDS levels and impedances you need. If you analyze the resistor networks used by the Bus-LVDS Xilinx I/O level or some of the older "LVDS" drivers in the various families, you'll find simple 3-resistor networks that make the rail-to-rail drivers look like a transmitter with 100 ohm differential impedance with the right voltage swing. You can alter the network to give you 173 ohms with a voltage swing appropriate to your receiver termination.

173 ohms all the way through make the signal clean at the receiver.
Reply to
John_H

All,

I suppose suggesting that the question could be answered in less than 10 minutes using a SIGNAL INTEGRITY simulator would just be silly?

I am absolutely amazed at how much time, money, and energy is wasted just because a SI simulator is "expensive."

One respin of a pcb is MORE $$$ than buying the SI simulator tool.

Mentor's Hyperlynx(tm) simulator is my favorite, but Cadence has their tool which might be more to some folks liking (it is integrated with the PCB layout stuff).

So, how about it? Invest in something that will save you enough money to pay for it the first time you do not screw up.

Submit a hotline webcase, and ask for a "what if" SI simulation. That way you will get a free example of (one) solution to your problem.

One comment: matching the transmitter impedance is a good idea, as a perfect match at the receiver is impossible (perfect may happen in textbooks, but not in real life).

Austin

Reply to
austin

You don't _need_ to match both transmitter and receiver. One or the other is good enough, provided the path between the driver and the cable has the same impedance as the cable, or this path is short. Cf. ECL logic, low output impedance, but can drive a properly terminated diff. pair. LVDS outputs are matched to the line to get a belt 'n' braces approach to reduce reflections, but it's not necessary to match the transmitter to the line.

Here's an app note which describes the output structures.

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HTH, Syms.

Reply to
Symon

Symon,

Xilinx must recommend the standard, tried and true, solution, we are not allowed to cut corners, as that leads to unhappy customers and lowers our sales figures while customers are trying to fix something they should have gotten right the first time.

LVDS is a standard. The transmitter is 100 ohms, the line is 100 ohms, the receiver is 100 ohms. They didn't do it this way because they were stupid: they did it this way for the reason I stated.

If you want to do SLVDS (Symon's Low Voltage Differential Signalling) be my guest.

Will SLVDS work? Most of the time, probably. The advantage of a standard is "set it and forget it" as there will be no problems unless you have done something wrong (like ignore the transmit match). Should simulate it, though.

Another example of this is where customers discover that simple LVCMOS works faster, and with less power to DDR SDRAM chips located close to the FPGA. Do we recommend it? No. Do people make a robust interface, that works just fine in production? Yes. But they have to do more work, to make sure they will be safe across all corners (silicon, voltage, temperature).

Austin

Reply to
austin

It is possible to match even Xilinx's hideous 10pF receiver pins. Here's an example from Xilinx's own consultant's website:-

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HTH, Syms.

Reply to
Symon

Did you read the OP's requirement? He's not driving a 100R transmission line, he's driving something with a different charactaristic impedance,

173R. So, the LVDS 'standard' won't work. Terminating the output will reduce his output swing. Are you sure in this application matching the output impedance is more important than a large signal swing? Cheers, Syms. p.s. Simulation is a good plan, I wonder where can you get a decent model for ribbon cable?
Reply to
Symon

Symon,

Yes, I know what the author of the post is trying to do.

Yes, Hyperlynx has built in models for a number of ribbon cables.

Without running the simulator, it is a complete waste of time to suggest anything as a "solution" to this question.

Now that I have spent three times longer than I would have solving it with the simulator, it appears that we have paid for the simulator, once again.

GET IT? (I know you do, Symon).

Austin

Reply to
austin

Here's some more links:-

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HTH, Syms.

Reply to
Symon

Symon,

Wrong solution.

Using the _DT internal differential termination, the driver will see 100 ohms in parallel with 5 pF (10pF in series with 10 pF).

If you SIMULATE this load, you will find that since the capacitance is directly across the 100 ohms, the receive signal is just fine.

Any reflections are absorbed by the 100 ohm driver (gee? I wonder what genius thought of doing this?).

The rise times from the driver are moderate, and adequate, so mis-matches don't jump up and make life difficult, and cross talk is reduced.

Some folks have lightning fast drivers, which cross talk like crazy, and even their "lower" input C looks awful, as a signal with 2X the rise makes even 3pF look really bad.

"The system is the solution." Driver, termination, line, receiver, all have to be considered. I know, you, personally have issue with the solution, but, face it, Virtex family has been an astounding success: and TO THIS DAY, we are the only ones with 65nm product, shipping (at all) production parts. ONE YEAR as of May 5th....

Think of all those sockets we are being designed into. All of those LVDS interfaces working. Literally tens of millions of them.

Do we have room to improve? Of course. But, any improvement is weighted against its benefits. Make the input less capacitive has no benefit (other than you would immediately post "see! I told you!" and I would not have to reply to this issue anymore).

What might be a better item to work on, rather than spend time on something that "ain't broke?"

Oh, did I mention how ecstatic we are that we have a one year lead on 65nm?

Austin

Reply to
austin

This kind of approach certainly isn't obvious.

The reflections will *certainly* be much better. Heck, the line can be probed and a good signal seen just about anywhere along the transmission line (assuming the probe doesn't introduce problems).

What should be noted is that - while there are no reflections and the end of the transmission line will see a superb voltage slow thanks to the R-only termination, this clean transition sees a series Zo impedance between it and the capacitor.

For a standard parallel Zo termination to a Zo characteristic impedance transmission line, the effective source is half the drive voltage through a Zo/2 impedance into the capacitor. If there is no capacitance, the transition is gorgeous at the receiver.

For the termination scheme suggested, the point where the transition line sees the resistance is the same half-voltage swing. Trouble here is that the equivalent series impedance to the capacitor is no longer fed by a half voltage with Zo/2 equivalent series impedance, but now a half voltage with a Zo series impedance.

If it's important to not have reflections, the R-only equivalent termination is superb. If it's important to have the high slew rate, the standard termination with the associated pin capacitance is the way to go because the reflection

*will* be absorbed by the transmitter's impedance if it's properly matched.

Signal Integrity *at the pin* is what's important and where a monte-carlo SI analysis will show which approach provides a cleaner interface in the end.

For this implementation where the speed is low, the extra 250 ps of RC time constant (it's C/2 for a differential signal) will probably provide excellent results.

- John_H

Reply to
John_H

No need to get py. There were many successful high speed designs before SI got the usable, affordable tools available today. Without a fundamental understanding of what DOES affect signal fidelity, we doom our engineering future to shotgun hacks at "trying" to get the signals to perform well.

Since we have the SI tools available now in a way they weren't available a decade ago, quick analysis of alternatives can be pursued. To suggest that fundamental knowledge be tossed out since there's a tool available is the short-sided view that often comes with the frustration of trying to communicate your point.

Please don't ask engineers to avoid learning the basics of delivering good signal integrity just because the tools are available to avoid doing the heavy mental lifting. When's the last time you gave someone $22 for a $17 charge expecting to get a $5 bill back and they stare at you like you're nuts. "But it's only $17." The crutch of calculators and cash registers have crippled much of a generation. Lets keep engineering steeped in fundamentals and use the tools as they're meant: as tools.

- John_H

Reply to
John_H

Hi Austin, I do so enjoy our little chats! I also know that you're a big fan of simulation, and I totally agree it's a great tool. (Oh, and BTW, thanks for the pointer, I didn't realise that some ribbon cables were included in Hyperlynx, that's cool! Although, I fear the OP's cable is not included.) My only comment is that some people are actually interested in the mechanisms at work. I'd say it's important to learn that first, and then use the simulator. All the best, Syms.

Reply to
Symon

We've been here before. I'll explain again. Remember that the OP is driving the line from a S3. So the 100 ohm driver has 5pf across it. Oh dear, the same reflection mechanism as at the receiver!

Of course they're moderate, they have to charge up a 5pF cap. That's not a good thing, no matter how you spin it! It's only adequate if your application needs a moderate rise time!?

So, I think on all my future high speed designs I'll add on extra capacitors to the drivers, you make it sound such a great idea! (Apologies for the sarcasm)

Wow, what brought that on? I'm sorry but for some reason I kept seeing Tom Cruise on the couch when I was reading that! Ever thought of switching to de-caf? :-) (Just kidding!!) Anyway, we've been through this before, we're never gonna agree, your loyalty to Xilinx is too strong for that (kidding again!), but anyone who's interested can search back through comp.arch.fpga and decide for themselves whether high speed outputs and receivers are compromised by pin capacitance. Cheers, Syms.

Reply to
Symon

Hi John, Neatly summarised! Thanks, Syms.

Reply to
Symon

Symon,

We agree to disagree.

I would hope that it is clear that the Xilinx solution works just fine.

There are just far too many working pcbs out there to suggest otherwise.

I have already agreed it could be better, but if it works, why bother?

As for loyalty to Xilinx, I am trying to be an engineer: facts, facts, facts.

Fact: input Z (and output Z) = 100 ohms + 5pf Fact: risetime is adequate for the job (too fast is actually a bad thing, too slow just mens you can't operate at very high rates, parts meet their specifications) Fact: Symon hates having any C in parallel with the termination. Fact: All terminations have some C. Fact: Symon and I do not agree.

Austin

Reply to
austin

John,

In no way did I imply that engineers should not learn about SI.

But, I can not require SI knowledge, either.

That is why we have IO standards (cookbook recipes).

Without a degree in E&M theory, I would argue that you can't really understand what is going on.

Well, a suppose a physicist might be capable of recognizing Maxwell's equations, but as far as I know, only those who have actually set up, and solved these equations, have the fundamental knowledge that is required.

There are many who have practical knowledge (experience), and that sometimes passes for understanding.

Anyone else is someone who is just pretending they have the knowledge.

And that is just fine: just as we can not ask that all users of FPGAs know everything about heat transfer, we recognize that the team who are using the FPGA will require some support for those specialties that they lack.

Austin

Reply to
austin

Symon,

I agree. For those for whom SI is a mystery, learn something today: go read up on SI.

Austin

Reply to
austin

Everywhere I look, I see unterminated transmitters:

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This makes sense: a 3.5 mA current source (transmitter) drops the proper 350 mV across the 100 ohm receive termination. If the transmitter also terminated in 100 ohms, you'd net half that swing. That's consistant with my observation that unterminated transmitters slew rail-to-rail on both pins.

But if the receiver terminates properly, there will be no reflections.

John

Reply to
John Larkin

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