LVDS in Cyclone-II

Hello folks,

I may be starting my first Altera design in a few years but I was disappointed to find that the Cyclone-II LVDS drivers aren't true differential drives: an external resistor network is needed to produce proper LVDS levels like in the "old days."

Does anyone here have experience with the LVDS drivers? I imagine I'll end up with 0603 resistors rather than a Bourns network, for instance. What have others used? Was there any problem driving these 2.5V pins at LVDS rates in power supply noise or EMI?

I don't have a huge count of output signals so it's reasonable from a space standpoint. The data sheet declares 640 Mbps LVDS transmit rates.

Also for receive... my glances through the Cyclone-II data sheet seem to indicate off-chip receive terminations are needed but I saw a post from Antti that said there were on-chip terminations. Did I miss something? Are on-chip terminations available for the Cyclone-II LVDS inputs?

The Spartan3E I/O solution is quite possibly better but pricing might push me back to brand A for this next design.

Any thoughts?

Thanks, John Handwork

Reply to
John_H
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The Spartan-3E I/O do not require external resistors for LVDS or RSDS outputs, which simplifies board routing, number of vias, reliability, etc.

For Spartan-3E LVDS or RSDS inputs, you can either use a 100-ohm external termination resistor or the internal DIFF_TERM resistor built into each pair, which is nominally 120 ohms.

Just FYI, we just recently released the following application note and reference design on Spartan-3E for LVDS display applications. It is even simpler on 4:1, 8:1, etc. designs.

XAPP485: 1:7 Deserialization in Spartan-3E FPGAs at Speeds Up to 666 Mbps

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--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs

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--------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.

Reply to
Steve Knapp (Xilinx Spartan-3 Generation FPGAs)

The Spartan3E LVDS approach is what I've grown to "expect:" a fully integrated solution. The Spartan3E should give great results for those signals in spite of the capacitance issues that nag at other engineers.

So now I wonder about the competitor's suboptimal solution.

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Reply to
John_H

Well, outputs don't have as much of a problem with Cpin as have inputs driven from a fast logic family; but you already know that :)

IIRC, the Lattice ECP2 have current mode LVDS drivers and ~8pF Cin.

I've been hoping that the removal of DCI from S3E has improved Cin; when Xilinx releases the S3E IBIS models, we can get a better idea.

It's interesting to contrast the datasheet C values for the two families:

Cyclone-II Cio 6 pF (typ) user I/O Clvds 6 pF (typ) user I/O with LVDS Cvref 21 pF (typ) user I/O with Vref function Cclk 5 pF (typ) global clock input

Spartan-3E Cin 3 pF (min) 10 pF (max)

Which makes no distinction between input only pins, I/O pins, global clock input pins, left/right side clock pins, dual mode config pins, Vref pins, dedicated config pins, etc.

Other S3E notes:

- the strangely low SSO limit (4) for the current mode drivers has reappeared for some of the S3E family, after improving in the latest S3 family SSO tables

- no IBIS models !!

- I haven't spotted any characterization data for the DT terminator accuracy; just the ~120 ohm number with no min or max limits

Brian

Reply to
Brian Davis

You could use the quad-smd's = 4 resistors in 1206 or 0805 ?

-jg

Reply to
Jim Granville

I could use "a Bourns network" or the like. I anticipate using 0603s because they're small, available, routable. Unless there's experience that says these tiny discretes should, indeed, be a resistor network instead.

I could use the quad-smd's. Is there a reason I should? Shouldn't?

I'm hoping more for tidbits of experience rather than good ideas.

Thanks for the thoughts.

Reply to
John_H

I noticed the SSO numbers but they don't affect me this round. The specs are "per power/ground pair" which is ample on the BGA packages (7 effective pairs per bank?) but still allows 8 SSOs on the wireframe parts (2 pairs ber bank). I interpreted that as LVDS pairs, so 16 signal lines per bank.

Oops.

I just remembered - there are only 4 banks on the Spartan3E. Yikes! The pairs per bank are 1.4x-2x the Spartan3 values so it looks like they may be legit.

I sure hope those SSOs get changed!!! ____

Larger Cyclone-IIs have 8 banks but they also have some strange single-ended / differential restrictions within a bank. Odd stuff. Maybe not a problem, but odd.

The Lattice parts are looking *nice* but are a bit low on memory for what I want to prototype. I was looking seriously at the new devices until I realized the breadth of the memory disparity. I could use a larger part with more memory but then the costs go up.

Reply to
John_H

Mainly it's a packing density issue. IIRC the pitch on the Quads, matches that of common TQFP packages. They are also on the right part of the price curve, and slash the resistor placement bill by 3/4.

-jg

Reply to
Jim Granville

When I'm doing a very dense board design, I typically use 0402 resistors because they can be tucked almost anywhere at will. IE, you aren't contrained to finding place(s) to set down one or more quad packs. Said another way, on average, I think I get better placement on densely routed boards using single 0402's. If you lower the density though, it probably makes sense to go to packs assuming your manufacturing house can make the boards without solder shorts on the packs.

Have fun,

Marc

Reply to
Marc Randolph

Which package did you plan to use and how many LVDS output pairs are required? The different SSO numbers on the quad-flat packages are purposely lower due to their merely average signal integrity. The BGA packages have superior signal integrity.

Here's how you would calculate the recommended limit using the data sheet values.

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Let's assume that you're using the TQ144 package, which has the equivalent of 2 VCC/GND pairs per bank (Table 92, page 133). Then, go to the LVDS_25 section in Table 93 (on page 134), indicating that you can have 4 LVDS _output pairs_ (emphasis included) per power ground pair. Multiply the values together to arrive at 8 LVDS _output pairs_ on a bank in the TQ144 package. Again, the SSOs are a recommendation, but let's keep it to 8 pairs, which equations to 16 I/O pins. There are only ~23 I/O on a package edge in the TQ144. The Input-only pins are not available as outputs. Also, SSOs are only for outputs. You can have as many LVDS inputs that will fit in an I/O bank.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs

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--------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.

Reply to
Steve Knapp (Xilinx Spartan-3 Generation FPGAs)

Well, the existing VQ100's aren't all that horrible; and if you can make this or the next generation available in a ground paddle QFP or QFN, the VQ100 size packages might even be better than the CP132's.

Toss in 2.5V-or-less I/O banks with better performance, and there'll be chocolate cake all 'round.

Well, those mysterious "fours" seem to have reappeared across the board again for the S3E differential drivers in VQ/PQ packages, with the spiffy well-balanced current mode drivers once again inconsistently assigned the same limit as have the older voltage mode, psuedo-differential, CMOS-with-resistors BLVDS outputs.

Those mystery fours also do not show the expected improvement in the smaller VQ package as do both the single ended standards and the latest Spartan-3 SSO limits for their current mode differential drivers.

In Spartan-3, the datasheet differential SSO's underwent the following series of gyrations:

- DS099-3 (v1.1) July 11, 2003 - no SSO lmits in datasheet

- DS099-3 (v1.3) March 4, 2004 - blank SSO table column for PQ/VQ packages

- blank SSO for all differential standards, PQ/VQ/BGA

- DS099-3 (v1.4) August 24, 2004 - deleted SSO table column for VQ/PQ packages

- all differential drivers, of any type, in BGA, have a listed SSO limit of 4

- LVDS_25_DCI input SSO limit of 4 in BGA

- DS099-3 (v1.5) December 17, 2004 - reappearance of VQ/PQ packages, with mysterious 4's across the board for the balanced current mode drivers for VQ/PQ/BGA

- VQ/PQ limit of 1 or 2 for BLVDS/PECL

- LVDS_25_DCI input SSO limit of 4

- DS099-3 (v1.6) August 19, 2005 - has more reasonable numbers for some of the current mode drivers, with better numbers for the smallest package as would be expected

- VQ/PQ limit of 1 or 2 for BLVDS/PECL

- LVDS_25_DCI input SSO limits have vanished

- DS099-3 (v2.0) April 3, 2006 - and even as we speak, your latest S3 datasheet has again improved the current mode driver SSO limits for the ones formerly stuck at '4'

For S3, Austin Lesea has indicated [2] that the LVDS_25_DCI numbers in the S3 datasheet SSO tables were there to handle the DCI terminator current; however, those DCI "fours" were removed in later SSO tables.

I'd avoid using many parallel DCI inputs in the same VQ/PQ bank [1,3] without first having some measurements of the internal DCI startup VCCO rail collapse.

Thankfully, S3E now has those approximately 120 ohm DT terminations.

Brian

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Reply to
Brian Davis

Thanks for the info, Steve. The only time I've had real troubles in the past was getting a feel-good for the improperly specified number of PCI signals per bank for the PQFP. The data sheet does a good job of presenting the SSO information (which isn't seen so clearly in competitors' literature).

For my current design I was looking at an LVDS translator on the front end implemented in a separate FPGA. The VQ or TQ package would make sense for such a low pin count application - 4 pairs in, 11 pairs out - but the SSO limits would exclude a simple flow-through design. In the VQ or TQ package I couldn't put all 11 balanced-current LVDS drivers on one bank.

The design will end up using Xilinx after all and a BGA package for the front end and the main functionality removes most of the limits.

PCI interfaces are something we've implemented a bunch in the past. The SSO numbers for the Spartan3E in the wireframe packages spread the interface out over at least 3 banks if those SSOs are to be believed. That's a bit more of a restriction than I'd expect but they are just wireframe packages. I'm hoping we're at the point soon where the price for wireframes aren't as attractive when compared to the "better" packaging.

- John_H

Reply to
John_H
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The current Spartan-3E data sheet does indeed show those mysterious "fours".

We're in the process of updating the Spartan-3E numbers and I expect the mysterious 4's to improve to 6's in the next data sheet release for LVDS, RSDS, and miniLVDS I/O standards. Effectively, this means that you can practically use all available I/O on a bank for LVDS, RSDS, or miniLVDS outputs (okay, you miss one or two pins on the PQ208).

The Spartan-3 SSO confusion that you mentioned happened due to the methodology we used at the time. Previously, the SSO numbers were generated strictly from simulation models, which always suffered from huge, conservative guardbands on new processes. Spartan-3 was one of the first commercially available 90 nm devices. The Spartan-3 SSO numbers started out very low and improved once we were able to back up the numbers with real silicon.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs

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--------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.

Reply to
Steve Knapp (Xilinx Spartan-3 Generation FPGAs)

Thanks for the update

Brian

Reply to
Brian Davis

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