Hi,
Can someone help me with this issue.
I am looking to build a serialer in a FPGA. Base frequence is 72MHz - 7 bits serialiser - so I need a LVDS frequence of
504MBps.I thought this wat not possible in a Cyclone device but just reads the app. note and it seems to be possible.
I have only some strong concerns because there is no timing budget and the IOB are not DDR IOB blocks.
Does any one has experience with this app. note ?
Thanks,
Eduard