LVDS as general differential input ?

Hello group, I have a design that implements Ethernet (10-base) without a PHY chip straight into an Altera Cyclone. Things are working fine mostly, but I'd like to improve the electrical interface if possible.

So far I've been using a transformer and two resistors into a standard

3.3V LVTTL pin. Levels were not optimal, so in some rare situations I lost connection.

I've tried something different now which seems to work much better: connecting the transformer directly to 2 pins configured as LVDS (+

100Ohm termination resistor).

I admit that this is somewhat of a hack, but I'd be happy about your opinion wether it's a really bad one, e.g. if the voltage levels (Vpp =

2.5V) out of the transformer might kill the inputs.

thanks, Sukandar

Reply to
sk
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You have GOT to be kidding.

I don't think normal ethernet signals will kill the inputs, but the datasheet should say explicitly what the safe voltage levels are. Transients are another matter. Why not just use a phy?

Also, what type of Ethernet uses simple differential signalling? I'm not really familiar with 10 megabit Ethernet, but fast Ethernet and Gigabit Ethernet use complex signalling that can't be detected with a simple differential receiver.

Finally, are you doing anything to set the common mode voltage? I would probably do something like this (use courier or similar to view the following ascii art schematic):

VCC ___ | / \ / 10 kOhms \ |

-----+ +--------------------+---lvds+ (||) / (||) \ 100 Ohms (||)transformer / (||) \

-----+ +--------------------+---lvds- | / \ 10 kOhms / \ | | --- GND

regards, Mac

Reply to
Mac

Hi Mac, thanks for your thoughts. I got the idea for a PHY-less implementation from

formatting link
where they do it without even a transformer but capacitive coupling and a few transistors.... There's also an article at EDN where this is discussed, although they're hinting at using an X485 type of transceiver to buffer the signal. My idea was to save on this too.

10-base has a simpler link pulse scheme (NLP) which (afaik) allows for simple differential signaling, whereas faster Ethernet uses FLPs that might differ here. I'll read up on this. Also thanks much for the ASCII art - it's been working fine without the two 10k, but I'll give it a try. As to the reason why - well, a chip saved is a chip saved....

best, Sukandar

Reply to
sk

My two bits for transient protection is a 3-element network on the left hand side of Mac's schematic, ie transformer _in_between_ transient protection network and FPGA. All three elements Transient Voltage Suppressors (basically a Zener diode or back-to-back Zener pair intended for this application).

(+Wire) == TVS ==== TVS == (-Wire) | TVS(bidir) | Ground(Circuit Board or Chassis)

The element in the common leg needs to be bidirectional, I think the other two can be either unidirectional or bidirectional. The top two would be rated so the transformer secondary doesn't exceed the FPGA max input, while the common element is rated so that a common-mode spike doesn't spark across the transformer.

but

X485= RS485? This buys you differential-to-single ended conversion, tolerance to overvoltage condition, tolerance to wide variation in differential signal amplitude. Newer devices provide slew-rate limited drive.

for

Don't remember enough about Ethernet, is there a minimum rate of guaranteed transitions ? Capacitive link _is_ simple and cheap, and I've seen it used in commercial high-speed networks (eg StarFabric).

the

Sounds like a good motivation to me. Still, RS485 might be the most effective from parts cost and count. Remember, for a commercial board in modest volumes, it costs 10 cents to put a part on a board, even a resistor that costs 0.1 cent for the part. Nowadays you can get capacitor arrays just like resistor arrays...

Regards,

-rajeev-

Reply to
Rajeev

Link pulses have nothing to do with actual data transmission. In both

10bt and 100btx individual link pulses are the same, only for FLPs they are spaced more closely. In 10bt link pulses are used to keep the link alive when there is no actual data packet transmission. For 100btx, FLPs are used in auto-negotation to decide which type of phy would be used as most 100btx phys also have a 10bt portion and can be connected to a 10bt or 100btx phy. Normal data transmission in 10bt is done with a manchester coded signalling scheme which can be recovered with a straight comparator or hacked up with a differential receiver as it's a two level signal with no appreciable ISI. In 100btx, the situation is quite different. It's a 3 level signal and there is considerable ISI so one needs a decent equalizer to recover the bits. Of course clock recovery and base-line wander are other issues to deal with.
Reply to
m

hi mk, thanks much for the explanation! (couldn't figure out what ISI stands for, though) thanks, sk

Reply to
sk

hi rajeev, thanks for your suggestions.

yes, I guess that's what they meant. I've just played a bit around with an ADM3491. Doesn't really add any functionality compared to my hack, but if it buys better protection I might end up using it.

Thanks, sk

Reply to
sk

ISI is Inter-Symbol Interference. Because of finite bandwidth, filtering, ringing etc, the analog level of a logic "1" will be different depending on whether it is preceded by a "0" or a "1". The preceding symbol interferes with the current symbol, hence the name. The word "symbol" is used instead of bit because there are many modulation schemes used in the communications world that encode multiple bits into each symbol. One symbol quals the (steady) information or state during one clock period.

Regards,

-rajeev-

Reply to
Rajeev

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