Hallo.
Some questions about Xilinx LUT6 FPGAs (my WebPack Toolchain is a little outdated, and the newer LUT6-FPGAs don't seem to show up correctly in fpga_editor).
- Is there really no carry-bypass option in LUT6-paths like the CYMUX(any,cin,1) living in LUT4 paths, apart from constraining the LUTs?
- SLICEMs and SLICELs always have a carry chain, while SLICEXs neither have a RAM nor a carry option?
- Within a CLB, SLICEMs are paired with SCLICEX (if there are SLICEXs in the device)? Sounds strange to me: If a LUT is configured to be dynamic, it is probably very likely that additional Carry logic isn't used, compared to static LUTs (with LUT4s, one rare reason to this is using the carry chain to implement a post-invert option for the RAM...). Have you ever seen a dynamic LUT6 really gain something in also using carry?
- What about production? Does it look like Xilinx might stop selling and developing new LUT4-FPGAs in the near future? I personally don't have enough overview about these two FPGA classes, so I can't see the detailed pros and cons.
Gruss
Jan Bruns