LUT input order

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Hey ppl

Is there a way we can have a control over the input order of the
LUTs...I see that eventhough we specify the inputs in the VHDL code
(I0, I1, I2 and I3), during the mapping process, the tool automatically
makes modifications and the routed design has a different order than
the one specified in the VHDL code....


                                               Thanks in Advance

Mr.B


Re: LUT input order
Why do you care?
The software tries to get the best routing, and may modify the LUT
inputs (and the LUT content)accordingly.
The LUT inputs can have individually different delays, and the software
knows that also.
Peter Alfke, Xilinx Applications

On Dec 2, 12:06 pm, snipped-for-privacy@gmail.com wrote:
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Re: LUT input order
Well, depending on how you define "best routing", swapping LUT pins may
or may not be a godd thing.

Cheers,
Jim
http://home.comcast.net/~jimwu88/tools /



Peter Alfke wrote:
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Re: LUT input order

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Yes, there is with a little bit of hand-waving.  The PAR software does
not lock inputs for a standard LUT, however it does lock inputs for an
SRL16E, because there the order of the inputs are important.  The SRL16E
behaves like a LUT4 as long as the write enable input is held low.  The
trick, therefore to locking the LUT pin assignments is to replace the
LUTs with SRL16E's with the enable control grounded.  I haven't tried
this on recent versions of ISE, but I know it worked in versions up
through 6.3.

Re: LUT input order
The "LOCK_PINS" constraint should take care of this. Check it out in
the constraint user guide. Depending on ISE version, you may need to
set it to different values.

HTH,
Jim
http://home.comcast.net/~jimwu88/tools /

snipped-for-privacy@gmail.com wrote:
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Re: LUT input order
When I was trying to lock down only 2 pins out of 4, I had no problems
for a while, then I couldn't get them to work; it might have been a
software change.  For this delay-matching circuit (to a first order
approximation) I had to use the LOCK_PINS:ALL constraint to map I0-I3 to
A1-A4... all 4 pins even though only 2 were critical.

There are very few applications that benefit from locking down the pins,
but they do exist.


Jim Wu wrote:
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Re: LUT input order
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Yep, and normally you also need to lock your routing for these rare apps.
Why not enter the twilight zone of 'directed routing'? :-)
http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0043_7.html
HTH, Syms.



Re: LUT input order
thank u folks....

John, which version of xilinx wer u working on? I am currently working on 8.1
and was trying to use the lock pins constraint, INST "lut_name" LOCK_PINS =
"I0:A1, I1:A2, I2:A3, I3:A4"; it pops up with a syntax error in da UCF file. I
dont know wer I am goin wrong. could u suggest me smthin on this....

thank u

Mr.B

Re: LUT input order
Mr B., could you please tell us why the LUT-address bit-order is
important for you.
Everybody knows that it is irrelevant in most cases. Yours must be
special...
Peter Alfke, Xilinx

Mr.B wrote:
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and was trying to use the lock pins constraint, INST "lut_name" LOCK_PINS =
"I0:A1, I1:A2, I2:A3, I3:A4"; it pops up with a syntax error in da UCF file. I
dont know wer I am goin wrong. could u suggest me smthin on this....
Quoted text here. Click to load it


Re: LUT input order
Hi Pete

I am tryin to permute the input order for that I need to fix the inputs
in a certain fashion.

Mr.B

Peter Alfke wrote:
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8.1 and was trying to use the lock pins constraint, INST "lut_name" LOCK_PINS =
"I0:A1, I1:A2, I2:A3, I3:A4"; it pops up with a syntax error in da UCF file. I
dont know wer I am goin wrong. could u suggest me smthin on this....
Quoted text here. Click to load it


Re: LUT input order
I suppose you know already that you can achieve the same result by
changing the content of the LUT, either by reconfiguration or even
dynamically by shifting in the new pattern serially.(SRL16)
Peter Alfke, Xilinx

On Dec 4, 4:31 pm, snipped-for-privacy@gmail.com wrote:
Quoted text here. Click to load it
8.1 and was trying to use the lock pins constraint, INST "lut_name" LOCK_PINS =
"I0:A1, I1:A2, I2:A3, I3:A4"; it pops up with a syntax error in da UCF file. I
dont know wer I am goin wrong. could u suggest me smthin on this....
Quoted text here. Click to load it


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