LUT, how to?

the tool will automatically infer distributed ram if you can do without a reset.

can you provide me some reference to the documentation that documents that? Moreover a LUT of 256 byte has an acceptable size or is too big? I know this is a stupid question, but I'm a newbye Thanks a lot

In fact you are right, this is what I was searching for, but I didn't know what was the better way to implement it. Now with your help I found it. Thanks Gio

Hi,

There's a few ways to do this. For Xilinx you would probably want to go through Coregen and implement a ROM with an init file.

You can also built the LUT entirely out of slices (as opposed to the specialize block memory structures) by using generic code. Below is an example that should work for probably any FPGA (Xilinx, Altera, etc). The LUT contents are define in-line, so it's not as nice as using a data file. (I'm lazy, so it's only an 8-entry 8-bit LUT).

Finally, for simulation only, you can use the Verilog block "initial" to and $readmemb to read from a file. This won't work if you want to synthesize to real hardware like the code below.

-- Pete

module lut #( parameter INPUT_WIDTH = 3, parameter DATA_WIDTH = 8 ) ( input clk, reset, input [INPUT_WIDTH-1:0] in, output reg [DATA_WIDTH-1:0] out );

wire [DATA_WIDTH-1:0] my_lut_values[2**INPUT_WIDTH-1:0]; wire [0:DATA_WIDTH*(2**INPUT_WIDTH)-1] my_lut_string;

// my string of values that will initialize the LUT: A0, B7, 15, C3,

// put the initialization string into the LUT array genvar i; generate for (i=0; i < 2**INPUT_WIDTH; i=i+1) begin: part_select assign my_lut_values[i] = my_lut_string[(i+1)*DATA_WIDTH-1 -: DATA_WIDTH]; end endgenerate

// do the lookup always @(posedge clk) begin if (reset) out

Unless you don't have the BRAM to spare, I'd use a BRAM for this. The easiest method is to use the core generator and an initialization file. Alternatively, you can instantiate a RAMB16 and set up the INIT attributes with your data.

Hi

I may be mistaken but, from where I sit, it seems that you are trying to implement a a 8:8 LUT (8-bit wide input, 8-bit wide output) ? If this is the case, I guess that a simple 256 bytes ROM would do the job.

Thanks a lot to everybody for your help, now my task is much more evident Giovanni

Get the data sheet for the chip you are considering using.

Most recent FPGAs have blocks of RAM. If you aren't using them for anything else then a big LUT/ROM is a great use for them. If you have better uses for all of the then maybe you should do something else for this part of the problem.

Giovanni, I am a big fan of using BlockRAMs for "unusual" applications. But here is one warning: All Xilinx BlockRAM are synchronous devices, which means, changing the address input has no effect on the output, until you apply the right clock edge. While conventional static ROMs may not require a clock, the Virtex and Spartan BlockROMs do ( and I think the competition uses a similar structure). In most cases the clocked operation is no problem, in some cases it is a big advantage, and sometimes it is a pain... Peter Alfke, Xilinx Application