I wanted to add to the thread at
But i got the message: replies are not allowed ? i really don't why? and who adds this constraint. as such i am opening this thread as a follow up to the previous posts at the above link. here is my message
I have just realised that Lattice LUT can be configured as 16x1 bit RAM ( , page 9). Is this an infringement to the above cited Xilinx Patents?
If not why Altera have not equipped their LUT with the same capability? They have instead in startix-3 the 640-bit Memory LAB(MLAB) which can be seen(i hope i am not mistaken) as 10 parallel altera LUTs. This is possible only thpugh in only half of the die
If the lattice LUT RAM mode infringes the XILINX patent, it should be the same (IMHO) with ALtera MLAB
The above in my opinion contradicts the claims that Xilinx is the unique FPGA device which provides distributed memory through their CLBs
any thought please?
Many thanks :)