LUT and latch in the FPGA

Use FPGA Editor to look at the diagram of a single slice. You'll see what logic and interconnection possibilities you have within the confines of a slice. In fact, you can even switch to editing mode and make connections manually. See if you can figure out how to pack your logic in there this way.

-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian

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Sorry for my carelessness--the device is xc2vp40-6-1152,and the two LUTs share the same reset signal. Let me introduce my design clearly: The function is a multiplier of 15*3,both multiplicators are 2's complement, say a[14:0] and b[2:0];b can be 0,+1,+2,-1 or -2(for ethernet,4D/PAM5).So the function is actually a mux,the output o[n] needs 5 inputs:a[n],a[n-1] and b[2:0].So I think use a 4-input(a[n],a[n-1],b[1:0]--change encoding) LUT and a D-latch(reset active when b is 3'h0) may save area in FPGA design.Are there some other good methods? In fact I do use FPGA Editor to generate a macro(since "clever" method did not work),but it brings out other questions -_-! First I generate a macro with only one LUT,but placer failed with a warning like "can not place function",I think maybe ISE considers the macro as a whole slice which contains only one LUT,so the design is too large to put in the device(remember there is 5k such functions here).But why the warning message appears at place stage and not map stage?And I think this problem is something like the RPM,right?But I could not find the reason why it is like this and how to avoid. Secondly I generate another macro fully using the whole slice(but my design uses only 3 of the 4--an eclectic solution).This time the warnings dissapear but it takes a very long time and routing process seems never convergent,so I stop it. Do you have any suggestion?Thanks a lot!

Best Regards, Ric Ma ASIC Department @Attansic Inc.

A new progress: I re-implement the design without LOC constraints(in translate stage) using my one-slice macro,after 12 hours of routing,the par failed and there's always

~~~~~~~ one slice ......

~~~~~~ CLB

Have a nice day!

Here comes the end.. The problem IS brought by the macro's reference comp(or something like that , I am not sure),because the placed macros(one slice each) are at the same position in the CLBs,and this reduces much routing agility . But in the design of the macro , I can not modify the attribute to let it not remember the position in the CLB . What I do is after the "map" process of the whole design , read in the ncd file in FPGA Editor and select all the macros and unbind them,then the tool will take all of them as ordinary components,and the PAR would not fail.Also , the area is saved by the use of these macros . In my design , the slice usage drops from 89% to 78%(XC2VP40). That's all,hope it helps , though seems just like talking to myself...Well, glad to be here and thank you for all the help , have a nice day!