HI! I'm a noob here.
I have to estimate and confront the area occupied by a LUT 4:1 and the area occupied by an FF. Can I count required gates? How many gates need a 4:1 LUT? and a FF?
Thanks in advance!
Cla
Why do you need to know? In an FPGA, the LUTs and flip-flops are tiny. Most of the area is used for interconnects (routing) and their configuration storage. But without routing the LUTs are worthless... So, what are you really asking? Peter Alfke, XilinxApplications
Because I have to estimate the area of different Functional Units, using the same parameter. For example,if I can choose from a FU that uses two 2:1 multiplexer and four FF and another FU that uses four 2:1 multiplexer and two FF, I'd like to prefer FU that occupies less area.
Sry for the english
Thanks
Not sure what you mean by "using the same parameter". Usually with FPGAs you want to estimate a designs by:
LUTS FFs RAM multipliers, PLLs, etc.
Having a single scalar number (like gates) to measure how much of the FPGA a functional unit consumes is a bad idea. It's best to think of functional unit size as a vector such as: (LUTs, FFs, blockRAM, multipliers)
You will run out of one resource before the others, depending on your design. You will typically run out of LUTs or RAM first, and FF's last. So in your example, the 2-LUT, 4-FF implementation is probably best.
-Jeff
I see.
But I have two algorithms and I have to estimate the term Area*Time (time of execution). How can I choose the best algorithm ( min Area*Time), if I haven't an unique parameter that rappresents the area?
-Cla
Count LUTs and FFs. It doesn't matter how much logic you put into a LUT, it still takes the same amount of area.
Maybe count RAM and multipliers too.
That's assuming you are trying to compare two implementations in a FPGA. If you are really targeting an ASIC technology, then you need to extract the logic and count the gates.
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Ok, thanks. I have to think about another solution..my problem remains unsolved
Cla
Claudio, your problem remains unsolved because you never told us what your problem is. If you want to select the best algorithm for a given FPGA family, that is an easy issue. If you want to compare different algorithms on different FPGA families and/or different manufacturers: more work, but still easy. If you are aiming for an ASIC: a totally different, and more difficult issue.
Don't ask for help, when you are unwilling to tell us your parameters! Peter Alfke
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