What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that push the power consumption to new lows in various "zero power" parts.
What design did you do that was very power sensitive, what parts did you use and how low did you get your power consumption?
Did you use any special tricks to get the power lower than you thought possible? Were you able to meet the goals you estimated before you did the design? In other words, any surprises?
Did you learn any limitations of the parts in what you could do in low power modes? Features you couldn't use or ways the parts didn't work as well as expected?
One thing that has occurred to me is that many RAM based parts have to be configured. This often takes a fair amount of power that might be a lot more than zero. Is there any way to stretch this out so the rate of configuration reduces the power level?
Rick