Low Power RTL Design

Hi All.. I'm now about to carry a low-power design, I've searched the net for low power design resources, but most of the resources on the web are focused on low power design tactics at the back end.

On the other hand, I didn't find any resources about good RTL design techniques for low power, except for the vague 6 pages in the RMM and some other papers that are much concerned with the power estimation rather than power reduction techniques.

Anyone has any information, links, or personnal expertise that can share it with me.

Best regards, Hosni

I have not seen any material other than device specific marketing push for low power design. Your device choice will likely be the biggest factor.

However for low design one the main things to try and do is to either minimise the logic size and compactness. The other area to consider are the amount of flip-flops that toggle, and the toggle rate, and to minimise both these factors. An example of these could be say a state machine where you have choice of the state machine encoding. Using binary, normal incremental, encoding you get an average greater than 1 flip-flop toggling for a machine that transitions to a new state every clock. Now you could use grey encoding for the same machine where only 1 flip-flop toggles. Taking a very simplistic analysis the grey encoded machine is likely to use less power.

It isn't a simple area as there are lots of secondary effects when you change something. The area power calculators for both Altera and Xilinx, and probably some others, so best to try out different approaches and see what wins.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.

you can greatly reduce power at the expense of performance by operating the FPGA at a reduced voltage. Austin Lesea can tell you more about it.

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401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com

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Hi Hosni,

There are many techniques for reducing your power consumption. Those at the RTL level have the highest possible impact, since you can change the behaviour of your system and make trade-offs that are not possible in later stages of the RTL-to-FPGA flow.

The "Stratix II Low Power Design Techniques" handbook section

provides some suggestions we have found to be helpful on Stratix II devices.

Most hardware designers were taught how to design when power wasn't such a big deal. This means that we often do things such as generate or read results even when we don't need them, since logically it doesn't matter (the downstream logic will be ignoring those inputs, etc.). If you can identify these cases and insert gating or clock control logic to stop unused pieces of logic from toggling when not needed, you can achieve a lot of power savings.

One example is RAMs. Users will often not specify a RAM read enable, thus the RAM will be executing a read every clock cycle. But you probably don't need the RAM result every cycle. By simply making an explicit read enable, you can greatly reduce the RAM power since every read operation initiates a pre-charge/dis-charge cycle within the RAM, and if the result is different than the previous cycle, causes downstream logic to wiggle too.

Regards,

Paul