I believe that connecting any unused i/os to gnd instead of leaving them floating helps in static power dissipation in generally any fpga. I am referring to the static power dissipated by the connection matrix in the fpga.
Am I correct?
Thanks.
-sanjay
You would be right,if the inputs were really floating, acting an antenna... Xilinx (and probably others too) has high-impedance weak pull-up resistors (really transistors) per default on each pin. Unless you have very strong crosstalk, those unused pins stay High, and cause no undesired dynamic or static power consumption.
Peter Alfke from home.
Some other manufacturers effectively disable unused inputs -- no possibility of totem pole current so no extra current.
Of course, take care of some special pins that depending on the manufacturer may not follow the standard rules -- they are special pins! For instance, check all the clock pins. And most importantly in life, ground TRST* hard (for those devices that have that optional JTAG pin). TRST* has an internal pull-up resistor so that by default the TAP controller is not forced to stay in the TEST-LOGIC-RESET state and a bit of noise or an upset can result in bad things.
-- rk, Just an OldEngineer "These are highly complicated pieces of equipment almost as complicated as living organisms. In some cases, they've been designed by other computers. We don't know exactly how they work." -- Scientist in Michael Crichton's 1973 movie, Westworld
Its interesting to learn about the disabling the unused inputs - how are the inputs disabled? I am assuming a FET. In that case wouldn't there still be some leakage especially in a 90nm process?
As far as gate leakage is concerned you worry about a few million sram bits in the FPGA but not about a few hundred inputs. After all that's only nA per Transistor. (BTW: Pulling the inputs to 0 does not with gate leakage either. There are as many input transistors connected to GND as there are conneced to VCC)
But it is important that the input gates are not switching because of the random input voltage. Disabling the input gates (e.g. by using a NAND instead of an inverter) reliably fixes that.
Kolja Sulimma
Agree, mostly. For some FPGAs, I've seen non-logic levels on the inputs result in on order of 1 mA/input. For some special pins like global clock pins, there could be on order of 50 mA for a non-logic level.
Cheers,
-- rk, Just an OldEngineer "These are highly complicated pieces of equipment almost as complicated as living organisms. In some cases, they've been designed by other computers. We don't know exactly how they work." -- Scientist in Michael Crichton's 1973 movie, Westworld
Thanks. Can you please elaborate on "by using a NAND instead of an inverter"? I am guessing that you are implying that the IO would be designed in this fashion? Or do you mean to actually write rtl logic to target into the fpga?
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