Logic required for multiplication

Hi

I would like to find out if there is some sort of an equation where we give the size of the two inputs and it tells us how many flip flops it is going to use to implement the multiplier function.

(It may be specific to the architecture of the chip but a rough estimate would do)

Thanks,

Reply to
spanchag
Loading thread data ...

In the newer FPGAs (like Virtex-II etc) you get ready-made multipliers that do not "cost" any flip-flops, but you can use pipeline flip-flops inside for free. For multiplier-intensive applications, you ask the wrong question. Multiplication is often implemented as a combinatorial function, without any flip-flops, except for pipelining. You can of course do it sequntially, and there is an endless number of option. But for speed reasons, most users prefer the "hard" combinatorial multipliers in the newer chipc. Peter Alfke

Reply to
Peter Alfke

For the multiplier function produced by compiling Verilog a 32 on the XC2S150 before I run out of columns. I've not tried fitting more than one.

Of course, those are full-parallel multipliers, and a serial one taking n cycles requires roughly 3n flip-flops, again arranged in columns to use the carry chain for the accumulator.

[my dev board has arrived; I may shortly start asking some incredibly newbie questions about why horribly-naive designs don't work ...]

Tom

Reply to
Thomas Womack

Thanks for your reply. I am working on something that will require more multipliers than the dedicated ones in the Virtex II, where I may have to implement some in logic and use the dedicated ones as well.

I was wondering if there is some sort of a computation method whereby we know the widths of the multiplier and the multiplicand and using the method we can compute the resources (like LUTs) the multiplication operation would use.

Reply to
spanchag

Assuming Virtex1/Virtex2-type logic cells (4-input LUT plus carry logic and Flip-Flop):

Generic combinatorial N x M multiplier takes ~ (N-1)*M cells.

Loadable KCM, also combinatorial, takes ~ (N/2-1)*(M+3) cells.

Scaling Accumulator multiplier, N clock cycles, takes M arithmetic cells. Depending on your infrastructure, you may have to count another N cells to serialize the multiplier, plus another N cells to store the LSBs that shift out.

If you haven't read Ray Andraka's page on multiplication

formatting link
yet, do so now.

I believe all of this also applies to Altera chips, except there the KCM is not loadable.

- Larry

Reply to
Larry Doolittle

There are many ways to multiply, and where you have lots of multiplies to do it may make sense to either time multiplex the existing multipliers or if it is for a sum of products use distributed arithmetic. We really need more information about your specific application in order to give you better guidance. Modern FPGAs can handle clock rates at

200+ MHz with carefully executed designs. Use that capability to fold the multiplicati> Thanks for your reply. I am working on something that will require

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com
formatting link

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

Reply to
Ray Andraka

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.