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Logic Accessible Clock

The Logic Accessible Clocks are entailed for example in

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I do not see much explanation of the concept. But, I would expect some when sys_clk_fb is registered by in-sync clk2. Sinse both clocks switch at the same time, the setup/hold time, the basics of HW design, are violated for sure!

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valtih1978
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en

This was something unique to DDR SDRAM implementation in a now obsolete FPGA family to allow for a local clock in the fabric. Improvements in modern FPGA families make this technique obsolete.

In this implementation the clock input does goes to the data input of a register, but the clock of this register is from a DCM 2X output and there is delay differences between the two that allows for this clock to be captured and then used as data with the logic.

Ed McGettigan

-- Xilinx Inc.

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Ed McGettigan

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