Hi all,
I'm about to convert the amplitude output from a Cordic to dB,
20*log(amp) that is. The output from the Cordic is 24 bits wide, the maximum value would thus be approximately 144.5 dB. It is sufficient with 12 bits resolution on the logarithm, 8 integer bits and 4 fractional bits.My idea is to create a look-up table out of BRAM in the FPGA, and since I want 12 bits resolution the size should not be larger than 2312 words (the largest value is 10010000.0111 which is equal to 2311 if the binary point is removed) each 12 bits wide. The problem has proved to be to create a clever address function though.
Any thoughts or ideas I have forseen? I'm sure this has been done before, but some Googling didn't really help me in the right direction.
Regards