Limitations of Xilinx coregen or limitations with using Xilinx primitives in synthesis.

Hi people, I was using an Altera FPGA for my WLAN MAC validation, In that one kind of the primitive memory components are named as 'altqpram'. If I need to use this memroy with different configurations (Ex:- different data bus widths) I can genrate one altqpram template using the Mega Wizard (GUI utility), and for my other memory cofigurations I can change the para- meter settings manually, by changing the file generated by megawizard.

Now, I am needing to migrate to Xilinx Virtex-II, I am using Xilinx - ISE on WIndows. When I use coregen to generate a primitive (memory), coregen creates several files. Among these are the netlist files for the core generated. Now, if I need a different memory component (Say, with bus width changed) I have to regenerate the component with a differnet name. I have not been able to find a way to get this configuration by manually altering the files generated by coregen (This doesn't look straight forward, atleast!).

Has somebody figured out a way of doing this?

Reply to
Swarna B
Loading thread data ...

Coregen lets me use the same name for a component I've modified. It just asks if I'm sure I want to overwrite my old files.

But I use Coregen manually (i.e. I invoke it myself instead of using Project Manager). Are you using Project Manager? If so perhaps by default it prevents you from overwriting an old component file because it doesn't know if another project is using that same file but expecting the old bus width, for example.

That's just a wild guess. Good luck.

Regards, Vinh

Reply to
Vinh Pham

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.