Hi people, I was using an Altera FPGA for my WLAN MAC validation, In that one kind of the primitive memory components are named as 'altqpram'. If I need to use this memroy with different configurations (Ex:- different data bus widths) I can genrate one altqpram template using the Mega Wizard (GUI utility), and for my other memory cofigurations I can change the para- meter settings manually, by changing the file generated by megawizard.
Now, I am needing to migrate to Xilinx Virtex-II, I am using Xilinx - ISE on WIndows. When I use coregen to generate a primitive (memory), coregen creates several files. Among these are the netlist files for the core generated. Now, if I need a different memory component (Say, with bus width changed) I have to regenerate the component with a differnet name. I have not been able to find a way to get this configuration by manually altering the files generated by coregen (This doesn't look straight forward, atleast!).
Has somebody figured out a way of doing this?