Legal Issues Reproducing Old CPU

This might not be the best group to ask, but I figured I would start here. I need to duplicate a 35-year-old CPU. Are there legal ramifications doing this?

For instance on OpenCores they have a partially-compliant C54x DSP core. I assume the partial compliance is in part not to run into licensing issues a nd have TI sue them. However, I need to duplicate the CPU's instruction set and associated cycle count exactly, so I'm pretty much going to copy the C PU using the existing documentation.

Thanks in advance for the help.

Reply to
ditiris
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Am 18.09.2013 06:30, schrieb snipped-for-privacy@gmail.com:

IANAL, but AFAIK, reproducing instruction set and cycle count exactly is OK, unless some of the instructions are patented. Patents expire after at most 20 years in any part of the world that I know of, so with a

35-year-old CPU you should be ok.

Philipp

Reply to
Philipp Klaus Krause

I think you need to be careful. While patents do expire (patents from

35 years ago expired after 17 years IIRC), copyrights generally do not. On the other hand it would be unusual for the owners of such old copyrights to pursue legal action against you unless you were making a lot of these devices. Still you're better off getting legal advice from someone who knows more about these issues, especially if you're intending to make significant money from this copying effort.
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Gabor
Reply to
GaborSzakacs

Is this an educational exercise or a product development case ?

Reply to
hamilton

Although I am not a lawyer... My understanding is that you can duplicate any hardware that is not patented. Few CPUs involve patents that can not be circumvented by not duplicating the exact circuit. One exception is the ARM7 (at least the 7). It has some feature of some interrupt instruction that requires a piece of hardware that is patented. That is the only example I know of.

Since you are looking at duplicating a 35 year old CPU, I think it would be pretty safe. Which CPU is it, if you don't mind?

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Rick
Reply to
rickman

Copyright does not cover a design, it only covers an expression. If you reverse engineered the chip and were making identical chips, that would be covered by copyright... But just duplicating the functionality, even by constructing a gate level copy of the CPU, would not be covered by copyright.

I am also not a lawyer...

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Rick
Reply to
rickman

Watch out! How are you going to have the same instruction set without "copying" it? If the instruction set itself is copyrighted (IIRC this was the case for the Intel 8080) you could have ompletely different underlying hardware and still infringe on the copyright. I seem to recall that some people worked around this by simply changing the instruction mnemonics...

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Gabor
Reply to
GaborSzakacs

No, the instruction set is a concept and is not copyrightable. The Z80 had the same instructions the 8080 had including the opcodes. They changed the nemonics because they could be copyrighted... possibly.

Don't confuse the design with the code. There are also issues with the size of the material "copied". A title of a book is not copyright protected for example. So you will find a NOP instruction in many CPU designs even though the 8080 had one. They even use the same nemonic in many CPU instruction sets.

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Rick
Reply to
rickman

I thought the mnemonics were copyrighted. Not the instruction set.

Rob.

Reply to
Rob Doyle

Which core ? If you are doing this to keep a legacy product alive, and keep off the chip-sales commercial radar ( ie no product names mentioned ) - then no one will know, and even if they did know, are unlikely to care.

Even more direct commercial replacements, of very old devices, seems to be fine, and you are a long way from this.

A good example is

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Here, they even mention vendor names and part numbers, and pitch directly for chip sales, but the vendors do not care, as they no longer have direct commercial offering.

-jg

Reply to
jg

(snip on duplicating an old CPU)

I suppose I wouldn't be surprised if someone would claim copyright infringement on a gate level copy, but it isn't likely that anyone would do that. The technology changes enough that gate level doesn't really apply. (Note that an FPGA implementation of the same netlist, implemented using LUTs, wouldn't be a gate level copy, anyway.)

Older CPUs liked to use pass transistors. Intel, more than many others, liked to use dynamic logic. (With a minimum clock frequency.) It isn't likely one would do either of those today.

You might get cycle accurate by wasting some cycles that would otherwise not be needed in current logic.

Do you need to duplicate the exact signals on the chip, or just the instruction level function and timing?

Neither am I. (IANALE.)

-- glen

Reply to
glen herrmannsfeldt

Of course neither of us are lawyers, but I'm pretty sure that gate a level copy would not be a violation of copyright. Copyright violation would require that you actually copy some feature of the chip. But then I guess you could argue that the gate inter-connectivity is a feature of the chip.

I guess this is above my pay grade...

That was *very* old CPUs... But then he did say 35 years. That would be 1980'ish, so integrated circuit CPUs were around and the pass transistor FF was used then.

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Rick
Reply to
rickman

I was under the impression that they still did; that a Core i7 for instance has for any given core a minimum frequency to keep it alive, otherwise you have to put it into sleep. I can't imagine they manage to put together a chip with a 3.6 GHz clock frequency out of classic CMOS.

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Rob Gaddi, Highland Technology -- www.highlandtechnology.com 
Email address domain is currently out of order.  See above to fix.
Reply to
Rob Gaddi

(snip on using pass transistors and/or dynamic logic)

They may or may not use dynamic logic, but many processors now have a PLL based frequency multiplier on the clock. That has a minimum clock frequency.

The 8086 and 8088 have dynamic logic with, if I remember, a 2MHz clock minumum. The 8080 is dynamic, but the Z80 is static. At some point, that was a useful advantage.

-- glen

Reply to
glen herrmannsfeldt

I suspect the reason it's only partially compliant is because it was too much work to make it fully compliant, not because of any IP issues.

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Tim Wescott 
Wescott Design Services 
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Reply to
Tim Wescott

Wow, lots of activity since I last checked. To answer some questions:

This is for business, not an educational exercise.

The chip is in the TI 9900 family (weird architecture).

I will need to reproduce all logical levels into and out of the chip with t iming faithful to the original chip (or as close as I can get it, divide is going to be an issue). A lot of the circuits on the board are old 54-serie s discrete logic, so those all get sucked in too, so we wind up emulating t he tri-state internal to the FPGA. Outside, we have lots of level converter s and discrete control to faithfully replicate the 5V tri-state.

The application is real-time, so I think that rules out software emulation. I explored that path a bit, but after reading up on SNES emulators (1991 3 .58MHz 16-bit CPU) and finding that most are heavily optimized and largely written in assembly, I figured HDL was a better cost-value-risk proposal. W hen I got to the part how most software emulators only work most of the tim e and they actually need a 3GHz multi-core CPU to accurately model the SNES hardware delays in all cases, I was really convinced HDL was the way to go ...

Software emulators are apparently fine legally, and I think that's a close corollary to what we'll be doing. Given that Tekmos has a business at all, we should really be fine.

However, we're still going to consult with a lawyer just to be sure.

Reply to
ditiris

Legal problems aside, if there's an emulator out there that's 100% accurate but for timing, and if you can do it this way, I'd run it fast enough so that the slowest instruction happens on time, then slow all the other ones down to match.

That gets difficult if some execution times are data-dependent.

As far as actual legal problems -- I think you're OK, but talking to a lawyer is a Good Idea.

First TI would have to care. Then they'd have to dare. Your biggest problem would be some TI lawyer trying to justify his pay by finding an encroachment, and you getting squished long before you can win just because they're so much bigger than you.

--
Tim Wescott 
Wescott Design Services 
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Reply to
Tim Wescott

When you say real time, you mean it not only has to be fast enough to meet any time deadlines, but you are concerned about the software being run having timing loops to interact with the rest of the hardware. Certainly that is possible, but it will be a lot of work.

I assume you have explored all the other solutions to the problem and you have decided that even though you can't spec out the time and effort for this one, you think it will be the fastest and least expensive?

Given that you have the rest of the board design at your disposal, I would think it might be easier to reverse engineer the board level design and add timing to it to offload that responsibility from the software. This may require a few changes to the software which I suppose is a bit more of an unknown.

Can you share any more details about the business need for this? I had a TMS9900 CPU board when I was getting started with CPUs and I designed a TMS9995 board for my own use. Yes, the architecture seemed a bit odd compared to other CPUs, but it was derived from a mini-computer where the idea worked well. Once on an IC, the memory bandwidth limited performance. But once the memory is inside the IC as well, performance will take off again. I bet this design could be moderately competitive in an FPGA if you wanted to run it as fast as it would go, likely 50 to

100 MHz.

Do you have adequate docs on the CPU? Which one are you using? I might still have a 9900 handbook somewhere around...

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Rick
Reply to
rickman

timing faithful to the original chip (or as close as I can get it, divide is going to be an issue). A lot of the circuits on the board are old 54-ser ies discrete logic, so those all get sucked in too, so we wind up emulating the tri-state internal to the FPGA. Outside, we have lots of level convert ers and discrete control to faithfully replicate the 5V tri-state.

If you are doing the CPU plus external logic, then you are even safer, as y our end result looks nothing like the original, nor can it drop into an or iginal socket.

What Clock Speed, Code and Data memory do you need to have, to match the or iginal ?

Reply to
jg

You might try to contact TI directly. I have found that the silicon companies can be quite co-operative given a some good reasons why you need to do this. Often helping customers even when they are not going to gain in future consideration. Hiding from them until they find you can be messy all round.

A gentle engineering approach perhaps passing the material you intend to disclose to them past a lawyer to understand pitfalls will often solve problems like this.

Walter..

Reply to
Walter Banks

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