Lattice's ECP5 - half of the program went MIA - WTF ?

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I've noticed that literally over night ordinary ( non-SERDES, non-automotive) members of ECP5 family is gone on Lattice's pages.

Questions:

1. Is there process advancement comming ( 40nm ->28 nm or similar)
2. Are we to see iCE50, MachXO4, ECP6 shortly ?
3. How much of this is caused by process advancement (like 28 nm becoming more cost-effective than 40nm for the purpose etc) ?
4. How much of this is caused by IoT and AI expansion ?
5. HOw much of this is caued by new names and offers ( Effinix, new Chinese names etc) ?

Re: Lattice's ECP5 - half of the program went MIA - WTF ?
On 29/11/2019 07:56, Brane2 wrote:
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Near panic - just about to design in LFE5U-45 in 256pin 0.8mm pitch BGA,

Still on the website today:
under the bold heading "0.8mm Spacing I/O Count/SERDES", 4th - 7th  
columns are parts with no serdes and not automotive.

Mouser had stock yesterday.

MK

Re: Lattice's ECP5 - half of the program went MIA - WTF ?
On Friday, November 29, 2019 at 2:56:19 AM UTC-5, Brane2 wrote:
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ive) members of ECP5 family is gone on Lattice's pages.
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 more cost-effective than 40nm for the purpose etc) ?
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se names etc) ?

I would ask what you have been smoking!???  I see parts that are not SERDES
 and not automotive.  They are in the same table as the rest of the ECP5 no
n-automotive parts, on the right.  I guess they are easy to overlook on the
 right side of the table.  

Not sure what an ICE50 would be other than a step backwards.  The original  
devices were the ICE65 made on a 65 nm process which was very quickly repla
ced with smaller, but more static power hungry ICE40 parts on a 40 nm proce
ss.  So ICE50 would be reversing course.  Maybe ICE28, but who knows?  

--  

  Rick C.

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Re: Lattice's ECP5 - half of the program went MIA - WTF ?
Dne petek, 29. november 2019 15.21.42 UTC je oseba Rick C napisala:
  
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ES and not automotive.  They are in the same table as the rest of the ECP5  
non-automotive parts, on the right.  I guess they are easy to overlook on t
he right side of the table.  

It looks like they've been arearangig those pages. Previous version had eac
h family version in separate table, with its own enclosure combinations.
I've seen new version without updated headers, which was fixed shortly afte
r...

  
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l devices were the ICE65 made on a 65 nm process which was very quickly rep
laced with smaller, but more static power hungry ICE40 parts on a 40 nm pro
cess.  So ICE50 would be reversing course.  Maybe ICE28, but who knows?  

I've meant to say next-gen. Didn't know that "40" signifies geometry size.
  
But while at it, with densities that low, geometry shrink is not always opt
imal, so who knows, they might do that or stay on 4onm buit use fundamental
ly different process etc.

Re: Lattice's ECP5 - half of the program went MIA - WTF ?
On Saturday, November 30, 2019 at 2:26:31 AM UTC-5, Brane2 wrote:
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RDES and not automotive.  They are in the same table as the rest of the ECP
5 non-automotive parts, on the right.  I guess they are easy to overlook on
 the right side of the table.  
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ach family version in separate table, with its own enclosure combinations.
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ter...
nal devices were the ICE65 made on a 65 nm process which was very quickly r
eplaced with smaller, but more static power hungry ICE40 parts on a 40 nm p
rocess.  So ICE50 would be reversing course.  Maybe ICE28, but who knows?
  
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.  
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ptimal, so who knows, they might do that or stay on 4onm buit use fundament
ally different process etc.

In the old days a shrink would be done on a design that reduced dimensions  
in the X and Y direction without changing the Z dimension features.  This w
as less work than a full scaling but didn't offer the full benefits (I migh
t have the terms switched).  I don't think they do that anymore as the deta
ils involved are more complex and since these processes are not at all on t
he cutting edge, but rather are well established "mature" processes at this
 point and so it is unlikely they would do anything other than move from on
e process to the next.  

I think there are issues with combining Flash with logic processes and that
 typically lags the state of the art by several generations.  The ICE parts
 don't have flash, they have RAM and one time programmable PROM.  

I believe the ICE parts are not about speed, rather cost, so presently the  
40 nm process is "good enough".  We will see what the recent competition wi
ll do for that.  

--  

  Rick C.

  + Get 1,000 miles of free Supercharging
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Re: Lattice's ECP5 - half of the program went MIA - WTF ?
On Saturday, 11/30/2019 8:54 AM, Rick C wrote:
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ICE parts were all about low power, especially ultra-low standby power.
Going to smaller nodes can be detrimental to standby power due to
increased leakage.  Trying to keep the standby power low when reducing
the geometry can lead to speeds that are almost the same as the larger
geometry, so unless you needed to pack more into the same die size you
don't really buy anything.  I also don't think that the ICE line is
central to Lattice's future business model.  ICE5 Ultra is likely the
end of the line for it.  (probably have to eat my words :-)


--  
Gabor

Re: Lattice's ECP5 - half of the program went MIA - WTF ?
On Saturday, November 30, 2019 at 9:32:11 AM UTC-5, Gabor wrote:
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SERDES and not automotive.  They are in the same table as the rest of the E
CP5 non-automotive parts, on the right.  I guess they are easy to overlook  
on the right side of the table.
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d each family version in separate table, with its own enclosure combination
s.
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 after...
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ginal devices were the ICE65 made on a 65 nm process which was very quickly
 replaced with smaller, but more static power hungry ICE40 parts on a 40 nm
 process.  So ICE50 would be reversing course.  Maybe ICE28, but who knows?
Quoted text here. Click to load it
ize.
s optimal, so who knows, they might do that or stay on 4onm buit use fundam
entally different process etc.
Quoted text here. Click to load it
ons in the X and Y direction without changing the Z dimension features.  Th
is was less work than a full scaling but didn't offer the full benefits (I  
might have the terms switched).  I don't think they do that anymore as the  
details involved are more complex and since these processes are not at all  
on the cutting edge, but rather are well established "mature" processes at  
this point and so it is unlikely they would do anything other than move fro
m one process to the next.
Quoted text here. Click to load it
that typically lags the state of the art by several generations.  The ICE p
arts don't have flash, they have RAM and one time programmable PROM.
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the 40 nm process is "good enough".  We will see what the recent competitio
n will do for that.
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I believe they can optimize a given geometry for power vs. speed, but I don
't know for sure.  The original 65 nm ICE65 chips had static power specs of
 low double digit uA.  The ICE40 products are 100 uA for most I believe.  T
here are some very small devices ~400 LUTs that are lower and one of the ne
w Ultra families get below 50 uA I believe.  Still, they took a hit on this
 moving to 40 nm.  With all the focus on low power in computing, do you thi
nk they can't move down a process node or two and retain the current static
 levels?  

--  

  Rick C.

  -- Get 1,000 miles of free Supercharging
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