Lattice Diamond and VHDL-2008

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I don't have any trouble getting the simulation (Active HDL) or  
synthesis (Synplify) tools to work with VHDL-2008, but the Lattice tool  
itself doesn't seem to understand it.  When Diamond analyzes the source  
files it complains of syntax errors.  The rest of the tool seems to work  
just fine and this doesn't stop me from completing the project.

I did an Internet search and found a post at eevblog.com about this from  
last year with no response.  I put in a ticket to Lattice.  I am using a  
slightly old version of the tool, 3.3 while the latest is 3.7 I believe.  
  I hope that's not my problem.  lol

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Rick C

Re: Lattice Diamond and VHDL-2008
On 6/16/2016 11:23 PM, rickman wrote:
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Wow!  This has been dragging out for a bit.  They replied saying the LSE  
tool can be set for VHDL-2008.  I wrote back that I don't have a setting  
for LSE.  They sent me a screen shot showing the setting in a dialog  
box.  I sent back a screen shot showing the same dialog box in my tool  
that doesn't have the LSE setting.  I've downloaded the most recent  
version of the tools and installed them before doing this.

Regardless, I'm not sure that LSE is the right setting.  That's an  
alternative synthesis tool, right, "Lattice Synthesis Engine"?  Is that  
what they use to parse the source when the design is "refreshed"?

Meanwhile, I also asked if the bitstream files were the same for the  
LFXP3E-3TN100C and LFXP3C-3TN100C and they said I should re-generate the  
bitstream.  The only difference should be that one uses an external 1.2  
volt core supply and the other has internal LDOs to work off 3.3 volts.  
Would that really result in any difference in the bitstream?  I don't  
want to have to regenerate the bitstream since it would require  
re-qualification.  I'm tempted to try it.  I don't have much confidence  
in the support.

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Rick C

Re: Lattice Diamond and VHDL-2008
rickman wrote:
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It's certainly worth a try, but if Lattice is anything like Xilinx,
there would be at a minimum a different device ID and the programming
tools would detect the difference and refuse to program the part.

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Gabor

Re: Lattice Diamond and VHDL-2008
On 7/8/2016 9:57 AM, GaborSzakacs wrote:
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I talked to a local FAE and he said he thought they used the same die  
with different bond out.  I can't get support to acknowledge they use  
the same bit stream, but maybe I can get them to say it is the same die.  
  If so, the ID would have to be the same.

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Rick C

Re: Lattice Diamond and VHDL-2008
Dne petek, 08. julij 2016 20.53.43 UTC+2 je oseba rickman napisala:
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FWIW, I have finally solved my Breakout Board problem and so now I can check the difference between XO2-7000HC/HE, which is of the same nature:

XO2-7000HC: ID= 0x012BD043
XO2-7000HE: ID= 0x012B5043

Interestingly, I had that old basic blinking leds demo for Breakout Board, that was done for HE chip and Programmer utility refused to burn it into HC chip.

But then I made new design with same Verilog file ( just regenerated power controller with IPExpress) for HC chip to test new board and that one I managed to burn into HC as well as HE chip.
Perhaps because I have had generated jedec as well as bitstream file this time and programmer managed to use jedec...









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