Hi, I should have probably sent this question to the VHDL newsgrp but since it has low activity, I've decided to send it here.
It is well documented that processes should be used to code sequential syst ems. The texbook gives an example of a D latch/flip flip. With FPGA tools, i have to use a process so the tool makes use of the available on-chip flip flops. But i wonder what if I describe a D latch and flip flop without the use of process: e.g.
1- latch: Q