Kingston module structure

I have inherited a nearly-working FPGA SDRAM controller but my testing shows I have got the structure wrong, partly due to lack of data on Kingston's site.

The module in question is the Kingston KVR133X64C3/1G.

The verilog I have inherited caters for 11 column bits, 13 row bits, 4 banks and two select lines. The module has sixteen chips on it which I thought might be eight bit each so there would have to be two chip select lines.

But my testing shows something wrong with the way I assign row/column/bank/cs. Maybe it is in fact 16 off 4 bit chips and just the one chip select but a test assuming that shows I'm still losing a bit somewhere.

So what is the structure of this module and does the column go out on A0-A9(,A11,A12) ? Googling throws up surprisingly little data given that I'm not out to buy them.

Jon

Reply to
jms019
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You could use the serial presence detect feature of the module in order to read out the device configuration. It's just I2C. The SPD ROM has this information.

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Jeremy

Reply to
Jeremy Stringer

The two addressing schemes I am aware of for 1GB DIMMs are: row A0-A12 column A0-A9,A11 row A0-A13 column A0-A9

In my experience, the first is more common, and is the one I normally expect on a 16 chip DIMM.

I really don't understand what you mean by "Maybe it is in fact 16 off 4 bit chips", so I can't address that. Micron supplies very good data sheets, so go get all the ones there for 1GB DIMMs. Even if your DIMM is not made by Micron, one of them probably matches what you have.

Reply to
Duane Clark

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