I have inherited a nearly-working FPGA SDRAM controller but my testing shows I have got the structure wrong, partly due to lack of data on Kingston's site.
The module in question is the Kingston KVR133X64C3/1G.
The verilog I have inherited caters for 11 column bits, 13 row bits, 4 banks and two select lines. The module has sixteen chips on it which I thought might be eight bit each so there would have to be two chip select lines.
But my testing shows something wrong with the way I assign row/column/bank/cs. Maybe it is in fact 16 off 4 bit chips and just the one chip select but a test assuming that shows I'm still losing a bit somewhere.
So what is the structure of this module and does the column go out on A0-A9(,A11,A12) ? Googling throws up surprisingly little data given that I'm not out to buy them.
Jon