Guys
I am trying to simulate the BSCAN_VIRTEX5 component. The Xilinx simulation guide, sim.pdf, says that you can instantiate a JTAG_SIM_VIRTEX5 in your testbench to control the BSCAN component.
So far I have been unable to get either the ISE simulator or the Aldec simulator to resolve the JTAG_SIM_VIRTEX5 component. I get this message in the ISE simulator: "Undefined symbol 'JTAG_SIM_VIRTEX5".
Can anyone tell me what library I need to include in my testbench to resolve the JTAG_SIM_VIRTEX5 component?
For reference I include my testbench VHDL.
Thanks
Pete
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LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.all; library UNISIM; use UNISIM.VComponents.all; use UNISIM.VPKG.all;
ENTITY jtag_interface_tb_vhd IS END jtag_interface_tb_vhd;
ARCHITECTURE behavior OF jtag_interface_tb_vhd IS
signal tdo, tck, tdi, tms : std_logic;
COMPONENT jtag_interface PORT( data_in : IN std_logic_vector(31 downto 0); clk_out : OUT std_logic; addr_out : OUT std_logic_vector(31 downto 0); data_out : OUT std_logic_vector(31 downto 0); we : OUT std_logic); END COMPONENT;
SIGNAL data_in : std_logic_vector(31 downto 0) := (others=>'0'); SIGNAL clk_out : std_logic; SIGNAL addr_out : std_logic_vector(31 downto 0); SIGNAL data_out : std_logic_vector(31 downto 0); SIGNAL we : std_logic;
constant tck_period : time := 1us;
BEGIN
JTAG_SIM_VIRTEX5_inst : JTAG_SIM_VIRTEX5 generic map (PART_NAME => "LX30") -- Specify target V5 device. Possible values are: "LX30", "LX50", "LX85", "LX110", "LX220", "LX330" port map ( TDO => TDO, -- JTAG data output (1-bit) TCK => TCK, -- Clock input (1-bit) TDI => TDI, -- JTAG data input (1-bit) TMS => TMS -- JTAG command input (1-bit) );
-- Instantiate the Unit Under Test (UUT) uut: jtag_interface PORT MAP( clk_out => clk_out, addr_out => addr_out, data_out => data_out, data_in => data_in, we => we);
tck_proc:process begin tck