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JTAG + PROM error!

Hi,

I have the problem that I can't communicate with my Xilinx XCF04S PROM through JTAG. The circuit setup is a "3.3V Master-Serial Configuration with 3.3V and JTAG with Platform Flash Prom" as here:

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To reduce the sources of error, I disconnected the JTAG input signals TMS, TCK, TDO to the FPGA, and connected the TDO directly from the PROM to the connector, therefore bypassing the FPGA. According to the PROM datasheet, the only pins that matters additionaly to the JTAG signals is the #CE pin (this pin is always low) and power pins. I checked with an oscillator the JTAG signals:

TCK

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TDI

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TDO

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TMS

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All JTAG signals toggel (i measured on the IC and connector to exclude any soldering problems). I noticed that TDI and TCK look very similar, however there is not short-cut between them

When I do an ID Check, i get this:

INFO:iMPACT:1578 - '1': Device IDCODE :

00001111111111111111111111111111 INFO:iMPACT:1579 - '1': Expected IDCODE: 00000101000001000110000010010011

I would like to have your opinions what you think the error is?

Thank you, Jidan

Reply to
jidan1
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I think the the problem lays on the TDO signal. The rising edge on TDO is abnormally slow and flat on the first pulse, here:

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. The TDO signal is connected directly from PROM to a Xilinx JTAG USB cable. Does somebody know why the signal is so flat?

Thanks,

JJ

Reply to
jidan1

here:

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The TDO

Any chance that the power was still coming up when you acquired the trace on your 'scope?

Reply to
Gabor

here:

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The TDO

No, that wasnt the case. I found out something interesting. When I touch the TDO signal with the oscillscope probe, the ID check and programming works!!!! And I think the probe induced a small parallel capacitance to GND that made this work. I have never found anything on this on xilinx application notes. The question is now what capacitance value is the best?

JJ

Reply to
jidan1

I don't know if that's going to help but I literally spent days on making the JTAG work and :

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This was after going through 3 flat cables which actually ALL were defective, lol. The 4th cable is starting to die, too. Sometimes I have to fold it just the right way to make contact. I need to get some more connectors. There must be some curse on those.

Also if you see funky waveforms on TDO this may be because when the chip's JTAG is idle, its output is tristated, but when it's active, its output is actively driving the cable. So, when it switches from active drive to tristate, it leaves only the pullup trying to fight with the cable capacitance. Hence you can see those waveforms on the scope. I don't think it's a problem though.

Xilinx oh Xilinx please put schmitt triggers on the TCK input...

Reply to
PFC

Oh yeah I forgot : last time this happened to me it was because the pressure I exerted while probing did restore the contact in the faulty flat cable connector...

Reply to
PFC

Thanks for the feedback. But in my case it was definatly the capacitor. I added a 100pF from GND to TDO on the JTAG programmer side and it worked. The cable is less than 30 cm and the frequency is 3/6 MHz. The JTAG programmer or Xilinx FPGA must be really sensitive.

Reply to
jidan1

What I want to understand, is why only the TDO signal? And if 30 cm was long or the cable was bad quality, then why didnt I see any distortions on the signals coming from the JTAG programmer?

Reply to
jidan1

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