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JTAG programing specs for XC18V01 PROM

Would anyone know where to get the JTAG programming specs (and programming times, page sizes, etc) for the XC18V01? I'd like to create an application for re-programming a 18V01 that takes as input the Intel Hex (MCS) and outputs JTAG bit banging. Xilinx recommends (app note 58 and 500) generating SVF or XSVF and using the XSVF player for the JTAG bit-bang. Unfortunately the memory requirements of this player are excessive.

So far most of my knowledge has been from studding the SVF file for the

18V01 that is generated by Impact - however - this isn't a good way to generate solid foundation for this project - and Xilinx has thus far been unwilling to provide these specifications.

TIA, Chris

Section of SVF file that program's a page:

RUNTEST 1 TCK; RUNTEST 1 TCK; // Loading device with a 'faddr' instruction. SIR 8 TDI (eb) ; SDR 16 TDI (0060) SMASK (ffff) ; RUNTEST 1 TCK; RUNTEST 1 TCK; // Loading device with a 'fpgm' instruction. ENDIR IRPAUSE; SIR 8 TDI (ea) ; RUNTEST 1 TCK; RUNTEST 14000 TCK; // Loading device with a 'fdata0' instruction. SIR 8 TDI (ed) ; SDR 2048 TDI (0100401004010000000000000000000000000004010040100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000) SMASK (ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; ENDIR IDLE;

XC18V01 BSD documents the following JTAG opcodes:

Attribute INSTRUCTION_OPCODE of XC1801 : entity is "BYPASS ( 11111111)," & "SAMPLE ( 00000001)," & "EXTEST ( 00000000)," & "IDCODE ( 11111110)," & "USERCODE ( 11111101)," & "HIGHZ ( 11111100)," & "CLAMP ( 11111010)," & "ISPEN ( 11101000)," & "ISPENC ( 11101001)," & "FPGM ( 11101010)," & "FADDR ( 11101011)," & "FVFY0 ( 11101111)," & "FVFY1 ( 11111000)," & "FVFY3 ( 11100010)," & "FVFY6 ( 11100110)," & "FERASE ( 11101100)," & "SERASE ( 00001010)," & "FDATA0 ( 11101101)," & "FDATA3 ( 11110011)," & "FBLANK0 ( 11100101)," & "FBLANK3 ( 11100001)," & "FBLANK6 ( 11100100)," & "NORMRST ( 11110000)," & "CONFIG ( 11101110)," &

Reply to
barnhart
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xilinx prom programming speca are not public and can not be obtained :(

antti

Reply to
Antti

Xilinx needs to go fsck itself.

Reply to
barnhart

Chris,

I have run into a similar problem with the Platform Flash. What you can do is look at a file located in the Xilinx tools directory called

C:\Xilinx81\xc18v00\data\xc18v01_pc20_1532.bsd

This is the ieee1532 bsdl file that describes the programming algorithm. for the xc18v00. Using this file and an understanding of the JTAG interface, you maybe able to decipher how to program your device.

Also it would be usefill to observe the JTAG signals of one of the Xilinx programmers while it is programming a device,. That is if you have access to one.

Between the bsdl file, the Xilinx softwaer you spoke of below and observing the JTAG bins I was able to impliment my onw program for the Platform Flash.

Good luck

Dave

(0100401004010000000000000000000000000004010040100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

(ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff

ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff

Reply to
David Colson

The BSDL file does not describe the programming algorithm. It just describes the boundry scan registers (some which are used for programming).

I would not call this decipher, but using the SVF file and the JTAG state machine you can extract how to program the device. The SVF file describes how to select the programming registers and the contents of these registers, the JTAG state machine describes how to shift data into boundry-scan registers.

e.g. if you toggle TMS and TDI according to this model:

formatting link

you should end up with what is described by the SVF given by the O.P.

Petter

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Reply to
Petter Gustad

Petter,

Actually the new ieee1532 bsdl file does describe the programming algorithm. It is required when you use Xilinx JDrive software to program a device. Please view the file: "xc18v01_1532.bsd". Not only does it describe to programming algotithmn, but it also gives the codes for the ISC instructions used for programming.

Dave Cols>

Reply to
David Colson

Now I understand why you used the term "decipher". Personally I find it more straight forward to use SVF.

Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
Reply to
Petter Gustad

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