I have a board using XC2VP20-6FF896c and two xc18v04 proms, seems Jtag have problem as: 1) Whenever there is a free-runnimg clock, the Jtag config fails. when the free-runnimg clock is turned off, config successfully. 2) Maseter seral mode never work, check cclk, it is alway there.
Could clock interference affect Jtag configuration? but I use the same design with virtex E, there is no problem. Appreciate any help on this problem.
I've seen EMI cause JTAG to fail configuration when using "flying leads". Making the leads shorter and twisting a ground with each signal helped.
Did the old Virtex E configuration have only one PROM. IIRC, in a multi-PROM configuration setting, the one electrically closest to the FPGA is the mcs file with a '0' in the name.
Yes, the old Virtex E configuration have only one PROM. what do you mean by "and twisting a ground with each signal helped"? Is that true to have a ground trace in parrallel with each signal?
"and twisting a ground with each signal helped"? Is that true to have a ground trace in parrallel with each signal?
I believe that magnetic coupling is a function of the loop area between the signal and a AC ground. If you have a wire hanging out in free space, it is my belief that it generates a lot of garbage and is susceptible to such. I believe the theory behind the twist is that it will reduce the loop area to a given magnetic field orientation. I believe E-field interference is reduced by a shield. Do not take my explanation of this too seriously.
Newman
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