JTAG port access in Cyclone

Okay..getting some own defined bitstream out of JTAG port when assigning something to "tdouser"...

But still unclear now what those JTAG IR exactly do:

0000001100 0000001101 0000001110

Any more documentation about this? Or is this some high-security risk NDA stuff?

thx rick

the documentation is almost non existant, I documented some useage of the altera bscan with some examples should be somewhere in

I was thinking that ony C (..001100) is the USER functions but hm you say D , E are as well ? no information about the D, E instructions, the quartus memory programmer uses C instruction that where I found it by doing trace on JTAG

antti

uups I used 1110 0x0E instruction not 0x0D as I previously posted

Antti

Correction (o;

instruction 0000001101 is CONFIG_IO as documented in BSD file...

Used 0000001100 last night for shifting out own shift register content successfully...

As the TCK/TMS/TDI signals are also available in the module... probably this would mean I could also use unused IR codes with own TAP controller?

Now have to wait for EBV Finland returning my other NIOS board for signal capturing (o;

greets rick

One strange thing...jtag discovery tool reports DR chain length of "7" for IR 0x00E:

Detecting DR length for IR 0000001110 ... 7

For 0x00C and 0x00D it shows normal "has to be defined" behaviour:

Detecting DR length for IR 0000001100 ... -1 Detecting DR length for IR 0000001101 ... -1

rick

jtag discovery tool? which one do you mean?

the 0x0E is defenetly "the" USER instruction it should be 'Open' when device is unconfigured..

the JTAG pins are not all directly accessible so you can not add your own Instructions but on the Altera you can monitor full traffic on the JTAG that passes by (that is not available on Xilinx at least pre V4)

antti

Using the jtag tools from the openwince project at sf.net. Great for boundary scan flashing and testing since you can add your own ir/dr definitions and get/set/reset individual boundary scan registers.

Hmm..might be NIOS2 config gets switched back residing in SPI during discovery (o;

How about Lattice?

rick

Erased SPI config memory..now correctly showing:

Detecting DR length for IR 0000001100 ... -1 Detecting DR length for IR 0000001110 ... -1

And both returning same preloaded 8-bit shift register:

Device Id: 00000010000010000100000011011101 Manufacturer: Altera Part: EP1C20F400 Stepping: 0 Filename: /usr/local/share/jtag/altera/ep1c20f400/ep1c20f400 Setting TCK frequency to 2 Hz jtag> instruction IR1100 jtag> shift ir jtag> shift dr jtag> dr

01101111 jtag> instruction IR1110 jtag> shift ir jtag> shift dr jtag> dr 01101111 jtag>

rick

device

look in MAX2 datasheet there are USER0 and USER1 defined !! I did not know !

Antti

Jedi, Antti,

Unfortunately the only official support of this nature is to allow your FPGA logic to access the SPI config port (rather than your host PC doing this). This is done by using either the EPCS serial flash controller or ASMI memory interface peripherals in SOPC Builder. Create an Avalon interface from your design to drive the peripheral you use and proceed from there.

Access to extending the JTAG chain in the device and driving these from the host PC are, at least for now, proprietary.

Jesse Kempa Altera jkempa -at- altera -dot- com

schrieb im Newsbeitrag news: snipped-for-privacy@g14g2000cwa.googlegroups.com...

ok, at least we now know 'what is official' -

To Altera - the ASMI and JTAG scan primitive has been used by different people outside the 'official' scope, partially by doing some RE on subject as the official documents hide some information about such useage.

hiding some features from the customers is not a good idea, IMHO. Actually I feel its rather stupid thing todo. You cant hide whats already partially visible. Any such info hiding attempts just make people pissed off. And it would not stay hidden anyway, nothing ever has.

most of the info to access JTAG primitive is there

ASMI direct useage without SOPC has been documented also several times by non-altera 3rd parties.

Antti

To: whom it may concern

Not only ASMI usage but also EPCS replacement has been documented and tested with several vendors. One vendors already did it by himself...I can post his repliy here if anybody wants (o;

I rather see it as a great feature and "kuul" making stuff like USER JTAG available and documented...doesn't it give some advantage over other vendors?

Speaking of hiding I don't really see also the point in removing the NIOS toolchain sources from ftp server, as done some 2 or 3 weeks ago...well...they were obsolete and software developers doing work on BSD systems don't have any chance to use the eval versions toolchain (o;

rick