Hi, I've a question regarding in-system programming of prom devices using the JTAG (ieee 1532) protocol. I implemented a programming algorithm based on the JTAG TAP controller state diagram (i.e. shown in xilinx app. note XAPP503). The implemented command sequences (i.e. for erase, program, read-prom, etc.) are taken from SVF files generated by the XILINX Impact tool and the corresponding BSDL-file based informations. Everything works fine (JTAG chain: with several XILINX FPGAs and corresponding serial & parallel config. proms [xcf04s, xcf16p]). The only problem is performance: its terribly slow. One point for optimization are the wait cycles given in the SVF, for example: 'RUNTEST 80000000 TCK;' means 80 seconds wait time for the erase command (which is very conservative). If I use the Impact tool the same command needs just a few seconds. Thus, there must be a method to observe the device status. In some other Xilinx papers I found the so called 'Instruction Capture Values' as part of the 'Instruction Scan Sequence' but I don't know how to implement the instruction scan sequence. Does a dedicated Instruction-code exist ? I can't find one in the BSDL file. Does anyone know how I can poll the device status (... or how I can get the 'Instruction Capture Values') ? Thank you in advance Ralf
- posted
17 years ago