JTAG access from user design in Altera FPGAs

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Hi,

does somebody know, how to access the JTAG port from a user design
(VHDL) in Altera FPGA (cyclone 4)?

TIA

Ludwig

Re: JTAG access from user design in Altera FPGAs
Ludwig Hgelschfer wrote:
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I don't know, if you can use the JTAG port as normal pins, as you can do
with some of the configuration pins after configuration, but you can use
a megafunction to communicate over the JTAG protocol with your entities:

http://www.altera.com/literature/ug/ug_virtualjtag.pdf

--  
Frank Buss, http://www.frank-buss.de
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Re: JTAG access from user design in Altera FPGAs
On 28.09.2012 12:44, Frank Buss wrote:
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Thanks a lot, that's exactly what I have looked for!

Ludwig


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