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JTAG access from user design in Altera FPGAs

Hi,

does somebody know, how to access the JTAG port from a user design (VHDL) in Altera FPGA (cyclone 4)?

TIA

Ludwig

Reply to
Ludwig Hügelschäfer
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I don't know, if you can use the JTAG port as normal pins, as you can do with some of the configuration pins after configuration, but you can use a megafunction to communicate over the JTAG protocol with your entities:

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Frank Buss, http://www.frank-buss.de 
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Reply to
Frank Buss

Thanks a lot, that's exactly what I have looked for!

Ludwig

Reply to
Ludwig Hügelschäfer

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