Jitter in DLLs vs PLLs

Is a side by side bench test of the DLL vs the PLL in a "real" situation where IOs and logic are switching, not just a quiet side by side back-off of a do-nothing design.

As frequencies increase, delays decrease, jitter fast becomes the number one problem in a design.

Realizing this, we have many tools, design notes, suggestions, and techniques to minimize jitter, and maximize performance.

Also,

is an excellent newly written description of the DCM (includes DLL) for Spartan 3 which also makes for good reading.

Aust> Just wondering if anyone can point me to some articals or papers that analyse

Austin,

Thanks, that's a decent and concise treatment of jitter. Not particularly easy to do.

Quick question that perhaps you (or anyone who's had experience w/ the RocketIO receivers) could answer...

Is the Peak-Peak Jitter tolerance spec'd in the rocketIO user's guide (.65 UI) spec'd in the 14-sigma fashion described in the xapp462 or is some measurement interval (such as loop lock time) assumed?

As it's given in the RocketIO User's guide, there's no BER, no sigma factor, and no specific measurement interval. Table 3-3, p.103 of the guide only says "peak-to-peak"

Any help/ experience would be greatly appreciated

Thanks,

--Josh Model MIT Lincoln Laboratory

analyse

Josh,

The p-p jitter for the V2P Rocekt IO is specified by using the 14 sigma case of broadband (DC to daylight, no filters) RMS jitter as measured by the Agilent DCA.

This method defines the "eye" as that which has 1E-12 BER or less extrapolated from the 14 sigma points (no actual BER measurements are done with this method).

As most folks know, if you filter out the low frequency phase noise (which is tracked out by the receiver) then the RMS jitter is even less.

Hence the claim that we are error free when used correctly is valid (as the 1E-12 contour was grossly pessimistic).

Aust> Austin,

Michael, Altera has published a document comparing PLLs to DLLs, specifically looking at jitter.

We also publish specs for PLL jitter in the appropriate device datasheet, so you can take a look at those as well.

Sincerely, Greg Steinke snipped-for-privacy@altera.com Altera Corporation

Greg,

Two things: first, the spec is not peak to peak, but cycle to cycle, so we do not "exceed" our spec as you erroneously state, and second, the jitter from the DLL is decidely non-gaussian so any statistical estimates are wrong. Can't "multiply by 6" or any other shortcut.

The peak to peak jitter is entirely random, but not a normal distribution as the taps are discrete, and the selection of the taps is from a digital control system.

The intrinsic jitter is not very interesting, as the "when busy" jitter of our part is 1/3 of yours under the same conditions.

Choosing the 2X output is also not entirely honest, as the 1X outputs have half the jitter (something you fail to mention, but we freely advise our customers of).

Other than that, we also have LeCroy equipment, and use it often. The

+/- 6 ps intrinsic measurement capability for jitter is selling you short, however, as the Wavecrest with its +/- 3 ps peak to peak worst case intrinsic jitter would make the PLL look better.

Aust>