Jitter and Static Timing Analysis

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View
A quick question, based on one of yesterday's threads on DCM jitter -

Does static timing analysis (timingan) factor in DCM jitter?

The Xilinx timing analyser help states under 'Guaranteed Setup and hold
requirements' that 'Timing will not include ....., and jitter into
guaranteed setup and hold requirements', but it also states elsewhere
that clock uncertainty is calculated from INPUT_JITTER and SYSTEM_JITTER
- I couldn't seem to find the clock uncertainty figure in my timing report.

So far, I've treated the timing analyser as a 'golden checker' for my
timing requirements - should I then be factoring in, say 200ps of jitter
in synth, p&r and timing analysis?  I'm running at 100MHz in a Spartan-3.

I'd also be interested in any other fine details of doing these analyses
  that you folks have to offer - in some of these cases, the devil seems
to be in the details :)  I'm semi-sure that I've read something
somewhere (I couldn't relocate it) about leaving a certain amount of the
timing budget left over - ie if you are 1 ps within budget, then you
cannot strictly guarantee that the device will work as expected, but I
couldn't find any recommendation of this sort in the Timing Closure
TechXclusive.

Thanks,
Jeremy

Re: Jitter and Static Timing Analysis
I've noticed that "Timing Uncertainty" is only shown for
paths that are printed in the error or verbose timing reports.
You won't see a global figure for each constraint.

A snippet:

Timing constraint: COMP "mv_ld_shft_l" OFFSET = OUT 8 nS  AFTER COMP
"fpga_sysclk" ;

 1 item analyzed, 1 timing error detected.
 Minimum allowable offset is   8.270ns.
--------------------------------------------------------------------------------
Slack:                  -0.270ns (requirement - (clock arrival + clock
path + data path + uncertainty))
  Source:               u_mv40_control_readout (FF)
  Destination:          mv_ld_shft_l (PAD)
  Source Clock:         fpga_sysclkb rising at 0.000ns
  Requirement:          8.000ns
  Data Path Delay:      8.227ns (Levels of Logic = 1)
  Clock Path Delay:     0.043ns (Levels of Logic = 3)
  Clock Uncertainty:    0.000ns

Note that the uncertainty is 0.000

If you want to see the figure used, select the verbose report
style with at least one path per constraint.

Jeremy Stringer wrote:
Quoted text here. Click to load it
hold

SYSTEM_JITTER
report.

jitter
Spartan-3.
Quoted text here. Click to load it
analyses
seems
the
I

--
Q: What is the most annoying thing on usenet and in e-mail?
A: Bottom-posting.
We've slightly trimmed the long signature. Click to see the full one.
Re: Jitter and Static Timing Analysis
OK, found it.  Thank you :)

Now to start plugging in figures...

Jeremy

Gabor wrote:
Quoted text here. Click to load it
 > [SNIP]
Quoted text here. Click to load it

Site Timeline