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Issues w/ 8 lane Aurora sample design

Hi All,

I'm trying to create a serial link operating at 2.5Gbps or higher using all 8 MGTs on the ML321 board. I modified a code that was used to create a 8 MGT link on a ML310 board. (Changed the MGT,Phase align, Clock instantiations/locations in the ucf file, and changed references in the verilog code accordingly) The Xilinx University Program's "Using High Speed Serial Links using Aurora IP' was used as a starting point. The code was modified so that a 1 MGT aurora module is instantiated 8 times

I keep getting these errors while trying to place & route in ISE:

ERROR:Place:482 - Bref comp BOTTOM_BREF_CLK_P locked incorrectly. Has to be PAD41 or PAD237 ERROR:Place:482 - Bref comp BOTTOM_BREF_CLK_P locked incorrectly. Has to be PAD41 or PAD237 ERROR:Place:482 - Bref comp BOTTOM_BREF_CLK_P locked incorrectly. Has to be PAD41 or PAD237 ERROR:Place:482 - Bref comp BOTTOM_BREF_CLK_P locked incorrectly. Has to be PAD41 or PAD237

I've checked to make sure that clock & MGTs are defined correctly in the ucf file, and referenced appropriately in the verilog code. The code seems to work on the ML310 board. Any ideas on what could cause such an error and how I can fix it?

Thanks, Billu

Reply to
billu
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billu schrieb:

Looks like you mixed up the top/botton MGTs and the corresponding BREF_CLKs. Remember, those are very dedicaded low jitter clocks with very resticted conectivity. Check again.

Regards Falk

Reply to
Falk Brunner

Just checked. I think they are ok ... 4 MGTs on the top use TOP_BREF_CLK (pins B14 and C14) and 4 MGTs on the bottom row use BOTTOM_BREF_CLK2 (pins AE13 and AD13)

The same code works for a ML310 board, so I'm guessing there some specific board related issue.

Any tips?

Thanks, Billu

Falk Brunner wrote:

Reply to
billu

billu schrieb:

Did you select the right device and packages in the project settings?

Regards Falk

Reply to
Falk Brunner

Yeah, definitely changed that.

I changed the settings to ML310 board (XC2VP30-FF896) to see if I can find any cues to the problem. I changed phase align module and clock pins in the ucf file and the compilation goes through fine. I cant really find any board specific settings/properties in the code

Thanks, Billu

Falk Brunner wrote:

Reply to
billu

Several things change in the source when you select a different clock source, at least when using the GT_CUSTOM core and Aurora2.3, assuming that is what the 8 lane sample uses.

The input clock signal itself needs to be tied to the the right input to GT_CUSTOM; that is one of the 4 B/REFCLK/2 pins.

The input REFCLKSEL needs to reflect the selection. It is '1' for B/REFCLK2 and '0' for B/REFCLK.

The generic (in VHDL) REF_CLK_V_SEL is 1 for REFCLK/2 and 0 for BREFCLK/2.

Reply to
Duane Clark

Hi Duane,

Thx for your response.

I modified the code to a 2 MGT configuration to make it easier to troubleshoot. A 2 MGT link setup using just top MGTs/Clock works fine, but I get the same error when I use a top MGT and a bottom MGT. Again, it seems to work w/ the XC2VP30-FF896. (changed settings in ISE and ucf file accordingly)

I'm only dealing w/ BREFCLK and BREFCLK2 b/c I want to operate in speeds excess of 2.5Gbps. I see a "REF_CLK_V_SEL" entry in the ucf file, which is set to '1'. In the aurora module (aurora_link.v; instantiated twice for the MGTs), I see a section of code commented as Reference Clocks. BREFCLK is tied to TOP_BREF_CLK, and the others are tied to ground. I'm planning on using TOP_BREF_CLK for the top MGT and BOTTOM_BREF_CLK2 for the bottom MGT.REFCLKSEL is set to 1'b0. I'm guessing it can only be set once, since the same core is being instantiated twice.

In the verilog code, TOP_BREF_CLK is assigned to top_BREF_CLK_i in the

1st module (top MGT) and TOP_BREF_CLK is assigned bottom_BREF_CLK_i in the 2nd module (bottom MGT). THe aurora module was generated in Core generator using BREFCLK and a MGT in the top row.

I tried to change those attributes, but I still get the same error. Any pointers?

Thanks, Billu

Duane Clark wrote:

Reply to
billu

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