ispLEVER Starter 6.0 FPGA Design Software Available

Lattice has released a new version of our downloadable ispLEVER Starter software, concurrent with version 6.0. Device support includes the 90nm LatticeECP2-50 and can be downloaded here:

formatting link

Regards, Bart Borosky, Lattice

Reply to
bart
Loading thread data ...

"bart" schrieb im Newsbeitrag news: snipped-for-privacy@j73g2000cwa.googlegroups.com...

are XP devices now suported in schematic?

antti

Reply to
Antti Lukats

Native Fedora/Debian linux versions?

Reply to
fpga_toys

Still without even the simplest free simulator?

Best regards Piotr Wyderski

Reply to
Piotr Wyderski

formatting link

Reply to
lb.edc

Piotr, In my opinion, if your design needs a simulator, then you better spend some money on a real good simulator. BTW, the full version of ispLEVER has ModelSim as simulator and the list price on Lattice's website is $695, and when you order online 'only' $495. For this price you get the OEM version of ModelSim - and this is by far the best deal you can get

Regards, Luc

Reply to
lb.edc

Any idea what the limitations of the OEM version of Modelsim are for the Lattice OEM version?

John Providenza

Reply to
johnp

John,

No X-Tracer

25-30% slower as full version (Altera has same limitation, Xilinx has even slower version)

That's it.

Luc

Reply to
lb.edc

Every design needs a simulator. Even as simple as that one from Quartus Webpack -- it is still infinitely better than no simulator.

Currently the best deal I can get is not to use Lattice or Actel parts -- the other vendors provide all the necessary tools.

Best regards Piotr Wyderski

Reply to
Piotr Wyderski

I use xilinx build in simulator for Lattice designs :) or ok usually I am not doing that either.

but sure a simulator is a nice a have feature (when it is available)

Antti

Reply to
Antti

Luc -

The last version of ModelSim/Altera that I purchased had a limitation of the number of instantiations you were allowed. If I started manually instantiating IO buffers for wide ram busses, I'd hit the limit and ModelSim would refuse to run.

John Providenza

Reply to
johnp

John,

There is indeed a 255-instance limit, so that is correct. However, as you can see from being able to run gate-level simulations, this limitation is not there when actually instantiating Altera cell primitives.

Thus, I'm not entirely sure how you ran into this limit, unless you wrapped the BIDIRs into something slightly higher-level.

BTW: Why did you instantiate those IO buffers? So far I've always been able to infer them.

Best regards,

Ben

Reply to
Ben Twijnstra

Piotr Wyderski wrote: > Still without even the simplest free simulator?

I use the free Icarus Simulator at:

formatting link
and I think it's great. Although it doesn't have a GUI interface, it's very simple and easy to use. I even use it in preference to the free simulators offered by some of the FPGA vendors, and have used it to develop a 2,000+ line Verilog program to implement the Elliptic Curve Factoring method an FPGA.

Ron

Reply to
Ron

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.