ise8.1 picking local instead of global clk routing?

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Hi,

I have an old asic prototype that was initially done using ise5.1 and a
virtex2, I'm now
moving to a virtex4 so I've moved to ise8.1i, initially targeting
virtex2

the design has five clks only one of them is really critical with a
fanout  of about 6000,
ise5.1 recognized all the clks and put them on global nets.

ise8.1i warns that the clk signal has non-clk connections (it does the
clk goes to an io for a debug interface) and it cannot fit it to a clk
template or something along those lines and puts the critical clk on
local routing and the design fails

is there a trick to getting ise8.1i to recognize the clock net?

regards,
-Lasse


Re: ise8.1 picking local instead of global clk routing?

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I would check this again.  Usually although the clock has local routing
to
the non-clock connections, global routing is used for the remaining
routes.  The warning can usually be ignored as long as you don't need
low skew on those few non-clock nodes.  Also on either virtex 2 or 4
you can use DDR output flip-flops to drive an IOB with a 1x clock
signal
without using non-clock routing (i.e. clock only needs to go to the
clock
input of the IOB, not the data path).  So if "the design fails" it may
be
due to some other issue.  Also note that both Virtex 2 and Virtex 4
have clock regions, which can become a problem with a lot of clocks
and may require some floorplanning.  If you have FPGA editor, you can
see how the clock actually got routed.

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