Hi, I use ISE8.1 (webpack) in Verilog. I try to use inout port. Sample code: module ....(... inout wire[7:0] data, ...); reg [7:0] buff; reg hiZ;
assign data=hiZ ? 8'bzzzz_zzzz:buff; .... endmodule
When I use xst to synthesis, and when I look at RTL logic , I cannot find tristate buffer in the circuit. And when I simulate with ModelSIM XE 6.0d (eval version), I got xxxx instead of zzzz.
Thank you, Sam
Thank you fro your respond. Then, how can I use inout port to conect to other module? Sam.
Sam-
This type of coding:
assign data = hiZ ? 8'hzz : (buf1 ? buff_1 : 8'hzz); assign data = hiZ ? 8'hzz : (buf2 ? buff_2 : 8'hzz);
works Ok, it's just not implemented using actual internal tri-states. Don't worry, tools handle it for you. ISE 7.1.04 may give warnings about "the following tristate(s) are NOT replaced by logic..." and I opened a webcase about that, but the word back is "just ignore".
-Jeff
Thank you, However, in ISE8.1 ,it also gives warning "Inout dosenot connect". What should I do? Sam.
There must be some dodgy code involved if it's taking the i/o out...
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