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ISE6.x/iMPACT, JTAG fails after any completed command

I am seeing a very strange behavior. Till last week I was using ISE6.1i03 succesfully in any design. Before I start a new design I did upgrade it to ISE6.3i03 and while debuging the new design's PCB I noticed when using iMPACT after any sucessfull device command like Erase, blank check or Program the XCF02S, or Programming the XC2S200E on board, the next JTAG command returns error (ERROR:iMPACT:1210 - '2':Boundary-scan chain test failed at bit position '1'). In the FPGA command case, the configuration is sucessfull (DONE goes high) but I/O pins still in Hi-Z. Mode pins are in JTAG. XCF02S memory is erased. When JTAG starts with this problem I have to cycle power in the design's PCB to have JTAG access again. Power supply (1.8V and 3.3V) is ok and no voltage dip is seen. I returned to ISE6.1i03 to see if there were something wrong with ISE6.3 under Windows XP+SP2 but there still the same problem (note that the old installed ISE6.1i03 was working perfectly under XP+SP2). I am using Xilinx original Parallel Download Cable-III. Now I am wondering if ISE6.3i installation did change some XP's system file (not returned by re-installation of ISE6.1i) that could lead to this error. I am currently two days under this fault and customer is already asking why a simple board test (to be sure all devices are working properly) cannot be done. Any clue will help a lot. Best regards,

Reply to
AugustoEinsfeldt
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Update: Did try to configure other FPGAs (XC2S100 and XC3S200) and it is working ok (any JTAG command and subsequent JTAG commands). So both WindowsXP+ISE6.1i03 (plus download cable) are working well and healthy. This lefts only the XC2S200E as guilty. It is the only common component in two different designs currently not responding to JTAG commands (and damaging communications with the XCF02S present in one chain). Curious observation is, in one design have a microcontroller+flash doing the configuration in slave serial mode and FPGAs is working well under this mode. I am going to give lot number for Xilinx guys in the hope to have any concerns about this silicon. So, I believe no answers from you will come and hope this case may help someone in some other design with this FPGA. Thanks,

Reply to
AugustoEinsfeldt

Solution found. The XCF02S was with its GND pin floating....Actually there was a PCB failure since the trace is almost touching the pad (I would say 1/10th milimeter apart). Problem found in my last attempt to find a solution, when I decided to look and verify every connection in the JTAG chain and on each pin of each device on the board using magnifying lenses. I did a verification before but not in the power pins... So, when something strange happens power pins verification should be near to the top of the check list.... Thanks for your attention.

Reply to
AugustoEinsfeldt

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