my basic design works perfectly. Now when I add a set of adders to the design I get timing errors in my design. I changed the PAR effort level from standard to medium andthe PAR completed successfully however when I test the design I see that my state machine gets stuck at one state and doesnt come out of it. It runs the first cycle of transitions susccessfully .However after that it gets stuck.What are the possible solutions which I can try. I changed the design to accomodate adders in different possible ways but still with no success. Thanks, D
You've already identified the problem "I get timing errors in my design". To 'fix' timing problems you need to start by performing static timing analysis. One of the things you need to perform static timing analysis is the output of the place and route which produces a file that has the results of the timing analysis that was performed by whatever place and route tool was used to run through the design. There are four basic types of numbers you're looking for Tsu, Tco, Tpd and T. The last one is the minimum clock cycle that your design will work at. The other three have to do with when inputs and outputs will be changing.
Once you've performed static timing analysis you will know when the input are allowed to change and at what time the outputs are allowed to change. These conditions must be adhered to both in a simulation environment or on an actual board.
If you have inputs that are inherently asynchronous to your FPGA clock then this means you'll find that you have a Tsu setup time that you are required to meet...but can't because the input is asynchronous to the clock. What you need to do there is first synchronize the signal with two flip flops and feed the output of the second flip flop to the rest of your design. The output of the first flip flop goes nowhere except for the input of the second flip flop.
Failure to perform static timing analysis and model these conditions appropriately is the primary cause for timing simulations to fail even though simulating the original code, 'works perfectly'. Similarly, failure to perform static timing analysis and putting the design into an actual part on a real board is the primary cause for 'flaky', 'unexpected' results that 'don't make any sense'. In both cases, if timing is violated then you can expect to see just about any symptom.
This analysis does NOT require use of simulation...in fact a simulator is completely useless for this analysis. Also, the above method is used for any design, it has absolutely nothing to do with the particular function you're implementing (i.e. 'adders', 'more adders', etc.). For that reason, "changed the design to accomodate adders in different possible ways" can only result in failure which is what you're seeing when you report "no success". You're going down the wrong path by changing the function so you'll never get where you need to go.
Hello KJ, I have added exactly one flip flop in between the asycnhronous inputs and the state machines since the asynchronous input is coming at a much lower rate. is it ok?
"What you need to do there is first synchronize the signal with two flip flops and feed the output of the second flip flop to the rest of your design. The output of the first flip flop goes nowhere except for the input of the second flip flop"
The 'lower rate' is irrelevant, if it's asynchronous you have no idea when it will come in relative to the clock that is sampling it.
When you run through the place and route, ISE will produce a timing report telling you all of the numbers (Tsu, Tco, Tpd and T) that I mentioned in my first post.
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here.
All logos and trade names are the property of their respective owners.