hi
since i'm pretty new ise i have a couple questions regarding timing:
currently i'm working on a design for an spi interface. so far everything is ok but now i need to work with 2 clock domains. from the microkontroller side i have an 100MHz clock and the spi side should run at 12 MHz (i should work with the ppc by the way so it's going to be integrated with edk).
when i was working with only one clock (the 100MHz one) my design synthesized at about 450 MHz. now when i connect the parts of my design that work with the different clock rates it suddenly drops to 80 MHz. The design is not that big (about 90 slices) so routing and placing should not be a problem. I assume this has something to do with the two clock domains. I wonder if ther is a state of the art way how to design with two clock domains. (right now i'm using registers. is there anything better or smarter? perhaps some examples ?)
another question is how does ise come up with those numbers? in synthesis there is no timing information or am i wrong?
and last is there any paper or maual on how to use the timing analyzer from ise? the other thing is the i need to place anrd route the design befor i can use that? so how can i find out the critical path from synthesis?
thanks urban