ise timing analysis + different clock domains

hi

since i'm pretty new ise i have a couple questions regarding timing:

currently i'm working on a design for an spi interface. so far everything is ok but now i need to work with 2 clock domains. from the microkontroller side i have an 100MHz clock and the spi side should run at 12 MHz (i should work with the ppc by the way so it's going to be integrated with edk).

when i was working with only one clock (the 100MHz one) my design synthesized at about 450 MHz. now when i connect the parts of my design that work with the different clock rates it suddenly drops to 80 MHz. The design is not that big (about 90 slices) so routing and placing should not be a problem. I assume this has something to do with the two clock domains. I wonder if ther is a state of the art way how to design with two clock domains. (right now i'm using registers. is there anything better or smarter? perhaps some examples ?)

another question is how does ise come up with those numbers? in synthesis there is no timing information or am i wrong?

and last is there any paper or maual on how to use the timing analyzer from ise? the other thing is the i need to place anrd route the design befor i can use that? so how can i find out the critical path from synthesis?

thanks urban

Reply to
u_stadler
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Easiest way to do everything on the fast clock and synchronize the slow clock as an input.

If that is not possible, then do separate modules for each clock with explicit synchronization.

google a bit

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-- Mike Treseler

Reply to
Mike Treseler

You should need to make sure that all paths that cross clock domains are protected against metastability, ie. adding pipelining of 2 or more clocks, depending on speed difference between clocks.

Then you'd create a TimingIGnore (TIG) constraint on those paths, grouped with the FROM-TO grouping constraint. See the constraint guide for info.

HTH,

-P@

Reply to
PatC

thanks for your answers!

but an open question is still how ise comes up with the clock speed after synthesis? as far is a read and learnd there is no timing information in that step and only a netlist is generated. or i'm i worng? how reliable are those numbers in real world? say if my design synthesises with 240 MHz will it run with 200 MHz on the fpga?

another thing is the timming reports. i searched the xilinx website and googled but i couldn't find some useful answers for me. is there a document or tutorial for those things because im a bit overwhelmed with all the information and i'm trying to figure out the important stuff....

thanks urban

Reply to
u_stadler

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