Hi.
When I try to see the RTL Schematic, Xilinx ISE hangs and it is not possible to stop it. Furthermore I get the following warning in the map report:
WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design.
But in the vhdl-description of split128bit, in128_k is definitly used:
------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all;
entity split128bit is port ( CLK100M : in std_logic; in128_d : in std_logic_vector(127 downto 0); in128_k : in std_logic_vector(127 downto 0); startin : in std_logic; out64_d : out std_logic_vector(63 downto 0); out64_k : out std_logic_vector(63 downto 0); startout : out std_logic; loadout : out std_logic; reset : in std_logic);
end split128bit;
architecture split128bit_arch of split128bit is signal state : std_logic_vector(1 downto 0) := "00"; begin -- split128bit_arch
process (CLK100M, reset) begin -- process if reset = '1' then out64_k '0'); out64_d '0'); startout