I'm still using ISE 8.2i. Yes, I know. But it's served me well and I live by the "if it works don't upgrade it principle."
"Served me well" until now that is. I may have found a bug. My FPGA works sometimes. Then I make certain innocent, harmless, neutral changes in an un-related area ... things stop working. Not an uncommon experience for FPGA engineers, I know.
I've possibly traced it to a high speed (200 MHz) counter which is reloaded using data from another clock domain . That data is stable when the counter reloads; but the point where it changes relative to the counter clock is uncontrolled.
I've checked the counter implementation using FPGA editor and noticed something curious about the LUT equations. When it works I get:
=((A1*A4)@A2); bel .
when it doesn't work I get:
=((~A2*(A1*A4))+(A2*(~A1+~A4))); bel .
for the same LUT, which is bit 0 of the counter.
A1 is the reload control A2 is counter Q[0] A4 is the load input from another clock domain.
The above two boolean expressions are equivalent; but why does FPGA Editor dump them in different formats and how do I verify what is actually in the LUT?
I'm wondering if a glitch is coming through the LUT when A4 changes
TIA