ISE 9.1 SAY YOURS OPINION

I've had no problems so far, 9.1.01i.

My design isn't huge - less than half an XC3S1600E - so my compile times aren't what are focused on with the speed improvements. Things did appear a little faster but that may also be because of my tuning the timing numbers recently to make things cleaner in my design.

One thing I did notice that looked different (maybe is was, maybe it wasn't) is when the timing was met (Timing Score 0) another quick step was also executed (Timing Score 0) perhaps as a visit to a "cleanup pass" that used to be a good part of the Place & Route. It's only an extra 15 seconds in my

8 minutes or so of Place & Route time. If it's a cleanup, it's much appreciated.

I don't use XST so I don't have any indication there. My flow comes in from SynplifyPro Edif and goes out with a promgen-generated .bin file. I had more of a hiccup (small as it was) with SynplifyPro 8.8 than with ISE

9.1.01i.

- John_H

Hi all,

ISE9.1i is faster than ISE8.2i and I noticed improvement for gate count (improvement of XST). Smart Guide is interesting but partition still have bug (like ISE8.2 with the "horrible" port.main.h crash !). Anyway, no hesitation, forget 8.2 and use 9.1i.

I've just started using ISE 9.1 sp1 and have mixed results. I don't have a lot of hours on it yet, but so far it seems to be a bit better than

8.1, but it still has serious bugs.

a) the 'compile' time seems to be a bit faster, my V4 design used to take about 3 hours, now its down to 2++ hours.

b) SmartGuide appears to be broken for my design. I get various system crashes or unable to route messages. If I do a pass without SmartGuide, it took about 2++ hours to Synthesize, Build, Map, Par, and Generate programming file. With SmartGuide, it died after over *** 5 Hours ***

c) Impact appears to have bugs in changing th target directory for ACE files.

d) I'm still seeing various complaints from the s/w about bad database or internal errors.

Xilinx still needs to do SERIOUS bug fixing.

John Providenza

By the way - the new "Project | Source Control" menu item looks compelling. I was able to generate a .tcl script which may be able to fully recreate the .ise file. I haven't tried to completely recreate a project from scratch, but the idea is compelling. I did export just the .tcl files without the extra suggested files and was able to import from that _impot.tcl script into a different directory to include all the paths I specified originally. I like it.

9.1.01i has at least one more bell or whistle!

I just got my full version of ISE (not webpack) and tried routing my current design. As part of the design, I use the DCM Standby workaround. I can import all the DCM Standby code into the GUI, but XST gives an error saying that there are missing modules. I opened a webcase, and my tech support person gets the same error that I do.

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Joe Samson
Pixel Velocity

I was just evaluating 9.1 (Webpack). I'm using small S3 and I have to wonder if Xilinx is just doing optimization(s) for high end parts. For my design, running in XC3S50, performance (both area and speed) degraded. I'm using a "make" driven flow and the settings (command line args and files) are the same for both 9.1/8.2 runs (actually I use a flow that I put togheter in 7.1 days or so).

Data from *syr:

8.2.03i - xst I.34: Number of Slices: 713 out of 768 92% Number of Slice Flip Flops: 428 out of 1536 27% Number of 4 input LUTs: 1306 out of 1536 85% Number used as logic: 1258 Number used as RAMs: 48

9.1i - xst J.30: Number of Slices: 696 out of 768 90% Number of Slice Flip Flops: 428 out of 1536 27% Number of 4 input LUTs: 1268 out of 1536 82% Number used as logic: 1220 Number used as RAMs: 48

Data from *par:

8.2.03i par I.34 Number of RAMB16s 4 out of 4 100% Number of Slices 699 out of 768 91% Number of SLICEMs 24 out of 384 6%

9.1i par J.30 Number of RAMB16s 4 out of 4 100% Number of Slices 753 out of 768 98% Number of SLICEMs 24 out of 384 6%

Data from *twr:

8.2.03i: Timing errors: 0 Score: 0

Constraints cover 100721 paths, 0 nets, and 5844 connections

Design statistics: Minimum period: 19.976ns (Maximum frequency: 50.060MHz)

9.1i: Timing errors: 1 Score: 325

Constraints cover 101771 paths, 0 nets, and 5659 connections

Design statistics: Minimum period: 20.650ns (Maximum frequency: 48.426MHz)

Run time for my flow:

8:2 420.14 real 343.23 user 6.20 sys 9.1 420.73 real 343.84 user 6.07 sys

I did not spend a lot of time in reading the new documentation for xst/ map/par to look for new switches/setting. If you are aware of eny please comment.

It seems the bit stream generated with 9.1 is running just fine in my applications (one data point, no temp/voltage/corners).

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Regards,
mmihai

Because of my 9.1i problem with synthesis, I'm back to 8.1i. Now the console window in the ISE GUI doesn't automatically scroll correctly. What should be happening is that new text appears on the bottom line of the console window, and the old text scrolls off the top of the window. Instead, the display is frozen in one place, and I have to constantly scroll down to see the new text. Is there a registry setting that controls this, because it doesn't seem to be a preference in 8.1i.

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Joe Samson
Pixel Velocity

I remember on service pack of the software that had display problems. Changing from a display that forces you to the bottom of the log (so far) when you're trying to review information so far was a HUGE improvement. If you try the latest service pack for 8.1 or consider going to the latest 8.x service pack and release you will be MUCH better off all around, not just for the display issue.

No major differences here between, ISE 8.2i and 9.1i Well got ChipScopPro 9.1 runnig on my Win2k3 Server. Which was not possible with ISE 8.2i

Bye Helmut

Thanks to everybody.... So seems that I'm not the only person having some sort of problem. I'm not the only person that has switched back to 8.x Thanks everibody.... ane please continue to write your comment here... We may help sombodyelse !

Francesco

for now i tried a V4SX55 and a 3S500E design and see some improvements on synthesis and par (both work quite well with the smartguide) ... still see those warnings about corrupt files and sometimes i have to close and re-open ISE because for some strange reason the editor stops accepting any input and by restarting it, i get back some response?

it also seems impossible to add xco files that are in the working directory to the GUI, from the moment they are in a sub-directory or other directory you can add them? the GUI seems a bit more stable and responsive...

I keep all the verilog source and xco files in the same Verilog subdirectory. In all previous versions, I could choose 'Add Source", then select all the files in the Verilog subdirectory. In 9.1i, the xco files can only be added using 'Add Copy of Source'. Apparently 'Add Source' is no longer good enough for xcos.

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Joe Samson

oh, that's a great step BACKWARDS.

-a

yes indeed, that is what the warning says ... but the strange thing even then i can't add them?

I have received a fix. The top level module, dcm_standby.v, uses a meta comment:

module dcm_standby ( CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, CLKFX, CLKFX180, LOCKED, DO, PSDONE, CLKFB, CLKIN, PSCLK, PSEN, PSINCDEC, RST )/* synthesis syn_noclockbuf=1 */;

This was OK in previous versions of XST, but not 9.1i. To fix it, remove the comment and place it in the code after the STANDBY and RINGOSC modules have been instantiated.

As for 9.1i breaking the 8.1i console window scrolling, I am out of luck; no working on 8.1i problems now that 9.1i has been released.

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Joe Samson
Pixel Velocity