Hi, everyone
I've been stuck on this problem for a couple of days, and still couldnt figure out how this happen. I have an XPS/ISE combined project. The part of ISE project is a hardware accelerator which is connected to powerpc system generated by XPS via dsocm. After I merged both projects in ISE and tried to implement it to fpga, the weird thing happened!!! My logic was almost removed by 25% after XIlinx Map. Firstly, I synthesized the whole project using XST. The synthesis report looks pretty right, about 30% of slice are consumed. And then I moved on to do translation, the report looks more or less the same. But after mapping, the logic utilization reduces to only 5%!!! Almost everything inside the hardware accelerator are removed. At the beginning, I assume there must be something wrong with the connection between the ppc_subsystem and the hardware accelerator. I triple checked the top level vhdl code but couldnt find anything wrong. I tried many many times re-mapping, I still got the 5% logic left. The hardware accelerator can function correcly and was verified by modelsim and can be correctly PAR, the logic utilization of which is around 30%. The ppc_subsystem can be correctly PAR as well, and consumes 4% of total fpga fabric. Both things can be synthesized but once after MAP, the total logic has been removed by 25%. I really cannot understand why the logic be removed even everything is in good connection.
Hardware Accelerator Only
--------------------------------------------------------------------------------------------------- Device Utilization Summary Logic Utilization Used Available Utilization Note(s) Number of Slice Flip Flops 8,485 27,392 30% Number of 4 input LUTs 5,421 27,392 19% Logic Distribution Number of occupied Slices 4,859 13,696 35% Number of Slices containing only related logic 4,859 4,859 100% Number of Slices containing unrelated logic 0 4,859 0% Total Number 4 input LUTs 6,387 27,392 23% Number used as logic 5,421 Number used as a route-thru 109 Number used for Dual Port RAMs 228 Number used as Shift registers 629 Number of bonded IOBs 147 556 26% IOB Flip Flops 1 Number of PPC405s 0 2 0% Number of Block RAMs 29 136 21% Number of MULT18X18s 48 136 35% Number of GCLKs 2 16 12% Number of GTs 0 8 0% Number of GT10s 0 0 0% Number of RPM macros 20 Total equivalent gate count for design 2,281,651 Additional JTAG gate count for IOBs 7,056
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Hardware Accelerator + PPC_subsystem
------------------------------------------------------------------------------------------------ Device Utilization Summary Logic Utilization Used Available Utilization Note(s) Number of Slice Flip Flops 1,370 27,392 5% Number of 4 input LUTs 1,486 27,392 5% Logic Distribution Number of occupied Slices 1,437 13,696 10% Number of Slices containing only related logic 1,437 1,437 100% Number of Slices containing unrelated logic 0 1,437 0% Total Number 4 input LUTs 1,796 27,392 6% Number used as logic 1,486 Number used as a route-thru 68 Number used for Dual Port RAMs 188 Number used as Shift registers 54 Number of bonded IOBs 4 556 1% IOB Flip Flops 2 Number of PPC405s 2 2 100% Number of JTAGPPCs 1 1 100% Number of Block RAMs 48 136 35% Number of GCLKs 2 16 12% Number of DCMs 1 8 12% Number of GTs 0 8 0% Number of GT10s 0 0 0% Total equivalent gate count for design 3,201,070 Additional JTAG gate count for IOBs 192
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Has anyone experienced this before?
Thanks in advance,
Yao