i'm just starting out with fpgas and i'm having what's probably a basic newbie problem. i have the following simple entity:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test1 is Port ( clk : in std_logic); end test1;
architecture Behavioral of test1 is begin process (clk) is variable i : integer := 0; begin if clk = '1' and clk'event then i := i + 1; end if; end process; end Behavioral;
and i have ISE webpack set to xc2vp2-6ff672 and in the ucf file i have:
NET "clk" LOC = "g14" ;
which i believe is the correct clock pin. when i synthesize that code, i get the following warning:
Synthesizing Unit . Related source file is "C:/temp/test1/test1.vhd". WARNING:Xst:647 - Input is never used. Unit synthesized.
what am i doing wrong?
thanks!