ise 7.1 Input clk is never used.

i'm just starting out with fpgas and i'm having what's probably a basic newbie problem. i have the following simple entity:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity test1 is Port ( clk : in std_logic); end test1;

architecture Behavioral of test1 is begin process (clk) is variable i : integer := 0; begin if clk = '1' and clk'event then i := i + 1; end if; end process; end Behavioral;

and i have ISE webpack set to xc2vp2-6ff672 and in the ucf file i have:

NET "clk" LOC = "g14" ;

which i believe is the correct clock pin. when i synthesize that code, i get the following warning:

Synthesizing Unit . Related source file is "C:/temp/test1/test1.vhd". WARNING:Xst:647 - Input is never used. Unit synthesized.

what am i doing wrong?

thanks!

Reply to
jeff murphy
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"jeff murphy" schrieb im Newsbeitrag news: snipped-for-privacy@g47g2000cwa.googlegroups.com...

1 designs with outputs are optimized to nothing, its empty !

2 do not use variable but signals if you can

antti

Reply to
Antti Lukats

#include

Well, you've declared i as a variable, and I doesn't get used anywhere, so my guess is that XST optimized it away. XST figures that you weren't doing anything useful with your counter.

-a

Reply to
Andy Peters

Reply to
raghurash

No output defined so everything is "optimized" away.

Please use

ieee.numeric_std.all;

instead of

ieee.std_logic_arith.all; ieee.std_logic_unsigned.all;

Rgds Andr=E9

Reply to
ALuPin

thanks, that was, ofcourse, exactly the problem. is there a faq on why i should use std.all instead of arith.all unsigned.all? ISE inserts the use statements for me... so i was just trusting that it put in the appropriate statements.

Reply to
jeff murphy

See here

formatting link

I wish Xilinx would get themselves up-to-date on this front. Numeric_std has been around a hell of a long time!

Cheers, Martin

--
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
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Reply to
Martin Thompson

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