I started a new project with an EDF file (generated from synplicit
pro), when i then translate, map and read the log file in ISE 6.2, i says my design has an equivalent gate count of 0?! It says basicall that at my top level the clock is sourceless - this makes sense becaus i dont have a pin constraints file, but when I arbitrarily assigned pin to the clock to see if that would sort it out, it doesn't. I als added "-u" to other command line options to try stop it from optimizin away my logic - again this didn't work.
The odd thing is when i synthesize (with synplicity) and export (edf the lower levels files and hierarchy, everything in ISE translates an maps fine - examining the generated log files for the individual lea cells and lower level hierarchy shows ball park correct figures fo equivalent gate counts
Any thoughts/help would be very much appreciate
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