1. Home
  2. Field-Programmable Gate Arrays
  3. ISE 6.2 - Bug or folly?

ISE 6.2 - Bug or folly?

Hello All,

I am using Synplicity Pro 7.5.1 to generate my edif file and then XST tools to do the mapping and PAR etc.

For my design, I am using a RAM16X1S i.e. 16-1 RAMs from the Xilinx low-level libraries. ISE 6.2 has this nice feature that reports resource usage i.e. No. of MUXF5s used etc in the MAP report (Could be done elsewhere in earlier versions). However, when I instantiate RAM16X1S, an equivalent number of Dynamic length shift registers are always indicated as used resources. This doesn't seem to make sense because there seems no need for shift registers in my design. Also, looking at FPGA editor indicates no Dynamic shift registers used. I am assuming that SRL16s are used in this case with variable address inputs. (Funny thing is no distributed RAM reported to be used as SRL16s)

Is it a bug or am I missing something? Please get back.

tEd

Reply to
Ted
Loading thread data ...

Ted,

The RAM16 is the same structure as the SRL16. It is the 16 bit LUT. Can be used three ways: as a LUT, as a RAM, as a SR.

You used it. I agree that the report is less than obvious.

Aust> Hello All,

Reply to
Austin Lesea

Hello Austin,

OK, so it is a mistake since the functionality of a dynamic SR and RAM is different even if they have the same I/O.

tEd

Reply to
Ted

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.